diff options
| -rw-r--r-- | util/inteltool/pcie.c | 54 |
1 files changed, 53 insertions, 1 deletions
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 67b0e1968f..53dc4c497e 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -172,6 +172,51 @@ static const io_register_t haswell_ult_dmi_registers[] = { }; /* + * All Skylake-S/H DMI Registers per + * + * 6th Generation Intel Processor Families for S-Platform Volume 2 of 2 + * Page 117 + * 332688-003E + * + * 6th Generation Intel Processor Families for H-Platform Volume 2 of 2 + * Page 117 + * 332987-002EN + */ +static const io_register_t skylake_dmi_registers[] = { + { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability + { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1 + { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2 + { 0x0C, 2, "DMIPVCCTL" }, // DMI Port VC Control + { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability + { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control + { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status + { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability + { 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control + { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status + { 0x34, 4, "DMIVCMRCAP" }, // DMI VCm Resource Capability + { 0x38, 4, "DMIVCMRCTL" }, // DMI VCm Resource Control + { 0x3E, 2, "DMIVCMRSTS" }, // DMI VCm Resource Status + { 0x40, 4, "DMIRCLDECH" }, // DMI Root Complex Link Declaration */ + { 0x44, 4, "DMIESD" }, // DMI Element Self Description + { 0x50, 4, "DMILE1D" }, // DMI Link Entry 1 Description + { 0x58, 4, "DMILE1A" }, // DMI Link Entry 1 Address + { 0x5C, 4, "DMILUE1A" }, // DMI Link Upper Entry 1 Address + { 0x60, 4, "DMILE2D" }, // DMI Link Entry 2 Description + { 0x68, 4, "DMILE2A" }, // DMI Link Entry 2 Address + { 0x84, 4, "LCAP" }, // Link Capabilities + { 0x88, 2, "LCTL" }, // Link Control + { 0x8A, 2, "LSTS" }, // DMI Link Status + { 0x98, 2, "LCTL2" }, // Link Control 2 + { 0x9A, 2, "LSTS2" }, // DMI Link Status 2 + { 0x1C4, 4, "DMIUESTS" }, // DMI Uncorrectable Error Status + { 0x1C8, 4, "DMIUEMSK" }, // DMI Uncorrectable Error Mask + { 0x1CC, 4, "DMIUESEV" }, // DMI Uncorrectable Error Mask + { 0x1D0, 4, "DMICESTS" }, // DMI Correctable Error Status + { 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask +}; + + +/* * Egress Port Root Complex MMIO configuration space */ int print_epbar(struct pci_dev *nb) @@ -335,7 +380,14 @@ int print_dmibar(struct pci_dev *nb) dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ break; - + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: + dmi_registers = skylake_dmi_registers; + size = ARRAY_SIZE(skylake_dmi_registers); + dmibar_phys = pci_read_long(nb, 0x68); + dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; + dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ + break; default: printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n"); return 1; |