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diff --git a/Documentation/mainboard/apple/macbookpro10_1.md b/Documentation/mainboard/apple/macbookpro10_1.md new file mode 100644 index 0000000000..a1a5061e2b --- /dev/null +++ b/Documentation/mainboard/apple/macbookpro10_1.md @@ -0,0 +1,55 @@ +# Apple MacBook Pro 10,1 + +This page describes how to run coreboot on MacBook Pro 10,1, also known +as 15'' Mid 2012 with Retina Display. + +```eval_rst ++-------------+-------------+ +| Model No. | Motherboard | ++-------------+-------------+ +| A1398 | 820-3332 | ++-------------+-------------+ +``` + +## Flashing instructions + +The board has one 8MB Macronix flash chip. To access the chip, you need to +remove the back cover. + + + +The flash layout of the OEM firmware is as follows: + + 00000000:00000fff fd + 00190000:007fffff bios + 00001000:0018ffff me + +## Working + +- 8GB model +- libgfxinit +- VGA ROM loading +- Integrated GPU +- Discrete GPU +- SeaBIOS, GRUB, TianoCore +- Linux 4.9, Linux 5.8 +- Wi-Fi +- Both USB ports +- Trackpad +- me_cleaner +- Integrated/Discrete graphics selection via nvramtool +- Camera +- Mic +- SD card reader +- Speaker +- usbdebug (the usb port on the right side) +- Backlight control via gmux (/sys/class/backlight/gmux_backlight), + works out of box on Ubuntu 20.04 + +## Untested + +- Thunderbolt +- FireWire + +## TODOs +- Support other memory configurations diff --git a/Documentation/mainboard/apple/mbp101_board.jpg b/Documentation/mainboard/apple/mbp101_board.jpg Binary files differnew file mode 100755 index 0000000000..ed7ee527d2 --- /dev/null +++ b/Documentation/mainboard/apple/mbp101_board.jpg diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 3260f73484..cec5ed03b3 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -9,6 +9,10 @@ This section contains documentation about coreboot on specific mainboards. ## AMD - [padmelon](amd/padmelon/padmelon.md) +## Apple + +- [MacBook Pro 10,1](apple/macbookpro10_1.md) + ## ASRock - [H81M-HDS](asrock/h81m-hds.md) diff --git a/src/drivers/apple/hybrid_graphics/Kconfig b/src/drivers/apple/hybrid_graphics/Kconfig new file mode 100644 index 0000000000..252373fb55 --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/Kconfig @@ -0,0 +1,3 @@ +config DRIVERS_APPLE_HYBRID_GRAPHICS + bool + default n diff --git a/src/drivers/apple/hybrid_graphics/Makefile.inc b/src/drivers/apple/hybrid_graphics/Makefile.inc new file mode 100644 index 0000000000..caef42a351 --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/Makefile.inc @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-$(CONFIG_DRIVERS_APPLE_HYBRID_GRAPHICS) += gmux.c romstage.c +ramstage-$(CONFIG_DRIVERS_APPLE_HYBRID_GRAPHICS) += gmux.c hybrid_graphics.c diff --git a/src/drivers/apple/hybrid_graphics/acpi/gmux.asl b/src/drivers/apple/hybrid_graphics/acpi/gmux.asl new file mode 100644 index 0000000000..bf6c8f0e44 --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/acpi/gmux.asl @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (GMUX) +{ + Name (_HID, EisaId ("APP000B")) + Name (_CID, "gmux") + Name (_STA, 0x0B) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, + 0x0700, // Range Minimum + 0x07FF, // Range Maximum + 0x01, // Alignment + 0xFF // Length + ) + }) + Name (_PRW, Package (0x02) { 0x16, 0x03 }) + Scope (\_GPE) + { + Method (_L16, 0, NotSerialized) + { + Notify (\_SB.PCI0.LPCB.GMUX, 0x80) + } + } + + Name (GMGP, 0x16) + Method (GMSP, 1, NotSerialized) + { + If (Arg0 == 0) + { + \GP06 |= Arg0 + } + } + + Method (GMLV, 0, NotSerialized) + { + Return (\GP06) + } +} diff --git a/src/drivers/apple/hybrid_graphics/chip.h b/src/drivers/apple/hybrid_graphics/chip.h new file mode 100644 index 0000000000..c7111f98a5 --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/chip.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _APPLE_HYBRID_GRAPHICS_CHIP_H_ +#define _APPLE_HYBRID_GRAPHICS_CHIP_H_ + +enum hybrid_graphics_req { + HYBRID_GRAPHICS_INTEGRATED = 0, + HYBRID_GRAPHICS_DISCRETE = 1 +}; + +#define HYBRID_GRAPHICS_DEFAULT_GPU HYBRID_GRAPHICS_INTEGRATED + +struct drivers_apple_hybrid_graphics_config { + bool gmux_indexed; +}; + +#endif /* _APPLE_HYBRID_GRAPHICS_CHIP_H_ */ diff --git a/src/drivers/apple/hybrid_graphics/gmux.c b/src/drivers/apple/hybrid_graphics/gmux.c new file mode 100644 index 0000000000..e3788b2436 --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/gmux.c @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> +#include <arch/io.h> +#include <device/device.h> +#include "gmux.h" +#include "chip.h" + +static int gmux_index_wait_ready(void) +{ + int i = 200; + u8 gwr = inb(GMUX_IOSTART + GMUX_PORT_WRITE); + + while (i && (gwr & 0x01)) { + inb(GMUX_IOSTART + GMUX_PORT_READ); + gwr = inb(GMUX_IOSTART + GMUX_PORT_WRITE); + udelay(100); + i--; + } + + return !!i; +} + +static int gmux_index_wait_complete(void) +{ + int i = 200; + u8 gwr = inb(GMUX_IOSTART + GMUX_PORT_WRITE); + + while (i && !(gwr & 0x01)) { + gwr = inb(GMUX_IOSTART + GMUX_PORT_WRITE); + udelay(100); + i--; + } + + if (gwr & 0x01) + inb(GMUX_IOSTART + GMUX_PORT_READ); + + return !!i; +} + +u8 gmux_pio_read8(u8 port) +{ + return inb(GMUX_IOSTART + port); +} + +u8 gmux_index_read8(u8 port) +{ + u8 val; + + gmux_index_wait_ready(); + outb(port, GMUX_IOSTART + GMUX_PORT_READ); + gmux_index_wait_complete(); + val = inb(GMUX_IOSTART + GMUX_PORT_VALUE); + + return val; +} + +void gmux_pio_write8(u8 port, u8 val) +{ + outb(val, GMUX_IOSTART + port); +} + +void gmux_index_write8(u8 port, u8 val) +{ + outb(val, GMUX_IOSTART + GMUX_PORT_VALUE); + gmux_index_wait_ready(); + outb(port, GMUX_IOSTART + GMUX_PORT_WRITE); + gmux_index_wait_complete(); +} + +u32 gmux_pio_read32(u8 port) +{ + return inl(GMUX_IOSTART + port); +} + +u32 gmux_index_read32(u8 port) +{ + u32 val; + + gmux_index_wait_ready(); + outb(port, GMUX_IOSTART + GMUX_PORT_READ); + gmux_index_wait_complete(); + val = inl(GMUX_IOSTART + GMUX_PORT_VALUE); + + return val; +} + +u8 gmux_read8(const struct device *dev, u8 port) +{ + const struct drivers_apple_hybrid_graphics_config + *config = dev->chip_info; + if (config->gmux_indexed) + return gmux_index_read8(port); + else + return gmux_pio_read8(port); +} + +void gmux_write8(const struct device *dev, u8 port, u8 val) +{ + const struct drivers_apple_hybrid_graphics_config + *config = dev->chip_info; + if (config->gmux_indexed) + gmux_index_write8(port, val); + else + gmux_pio_write8(port, val); +} + +u32 gmux_read32(const struct device *dev, u8 port) +{ + const struct drivers_apple_hybrid_graphics_config + *config = dev->chip_info; + if (config->gmux_indexed) + return gmux_index_read32(port); + else + return gmux_pio_read32(port); +} + +void gmux_dgpu_power_enable(const struct device *dev, bool enable) +{ + if (enable) { + gmux_write8(dev, GMUX_PORT_DISCRETE_POWER, 1); + gmux_write8(dev, GMUX_PORT_DISCRETE_POWER, 3); + } else { + gmux_write8(dev, GMUX_PORT_DISCRETE_POWER, 1); + gmux_write8(dev, GMUX_PORT_DISCRETE_POWER, 0); + } +} + +void gmux_switch(const struct device *dev, bool dgpu) +{ + if (dgpu) { + gmux_write8(dev, GMUX_PORT_SWITCH_DDC, 2); + gmux_write8(dev, GMUX_PORT_SWITCH_DISPLAY, 3); + } else { + gmux_write8(dev, GMUX_PORT_SWITCH_DDC, 1); + gmux_write8(dev, GMUX_PORT_SWITCH_DISPLAY, 2); + } +} diff --git a/src/drivers/apple/hybrid_graphics/gmux.h b/src/drivers/apple/hybrid_graphics/gmux.h new file mode 100644 index 0000000000..075f9b6ca5 --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/gmux.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef DRIVERS_APPLE_GMUX_H +#define DRIVERS_APPLE_GMUX_H + +#define GMUX_PORT_VERSION_MAJOR 0x04 +#define GMUX_PORT_VERSION_MINOR 0x05 +#define GMUX_PORT_VERSION_RELEASE 0x06 + +#define GMUX_PORT_SWITCH_DISPLAY 0x10 +#define GMUX_PORT_SWITCH_DDC 0x28 +#define GMUX_PORT_DISCRETE_POWER 0x50 +#define GMUX_PORT_MAX_BRIGHTNESS 0x70 +#define GMUX_PORT_BRIGHTNESS 0x74 +#define GMUX_PORT_VALUE 0xc2 +#define GMUX_PORT_READ 0xd0 +#define GMUX_PORT_WRITE 0xd4 + +#define GMUX_PORT_INTERRUPT_ENABLE 0x14 +#define GMUX_INTERRUPT_ENABLE 0xff +#define GMUX_INTERRUPT_DISABLE 0x00 + +#define GMUX_BRIGHTNESS_MASK 0x00ffffff +#define GMUX_MAX_BRIGHTNESS GMUX_BRIGHTNESS_MASK + +#define GMUX_IOSTART 0x700 + +u8 gmux_index_read8(u8 port); +u8 gmux_pio_read8(u8 port); +u8 gmux_read8(const struct device *dev, u8 port); + +void gmux_index_write8(u8 port, u8 val); +void gmux_pio_write8(u8 port, u8 val); +void gmux_write8(const struct device *dev, u8 port, u8 val); + +u32 gmux_index_read32(u8 port); +u32 gmux_pio_read32(u8 port); +u32 gmux_read32(const struct device *dev, u8 port); + +void gmux_switch(const struct device *dev, bool dgpu); +void gmux_dgpu_power_enable(const struct device *dev, bool enable); + +#endif /* DRIVERS_APPLE_GMUX_H */ diff --git a/src/drivers/apple/hybrid_graphics/hybrid_graphics.c b/src/drivers/apple/hybrid_graphics/hybrid_graphics.c new file mode 100644 index 0000000000..7ec29fc345 --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/hybrid_graphics.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> +#include <option.h> +#include <device/device.h> + +#include <southbridge/intel/common/gpio.h> +#include <console/console.h> +#include "chip.h" +#include "gmux.h" + +static void enable_dev(struct device *dev) +{ + const struct drivers_lenovo_hybrid_graphics_config *config; + enum hybrid_graphics_req mode; + u8 ver_major, ver_minor, ver_release; + u32 version, max_brightness, brightness; + + /* Don't confuse anyone else and disable the fake device */ + dev->enabled = 0; + + config = dev->chip_info; + if (!config) { + printk(BIOS_INFO, "Hybrid graphics: Not installed\n"); + return; + } + + version = gmux_index_read32(GMUX_PORT_VERSION_MAJOR); + ver_major = (version >> 24) & 0xff; + ver_minor = (version >> 16) & 0xff; + ver_release = (version >> 8) & 0xff; + max_brightness = gmux_index_read32(GMUX_PORT_MAX_BRIGHTNESS); + brightness = gmux_index_read32(GMUX_PORT_BRIGHTNESS) + & GMUX_BRIGHTNESS_MASK; + + printk(BIOS_INFO, "gmux version: %d.%d.%d\n", + ver_major, ver_minor, ver_release); + printk(BIOS_INFO, "gmux max brightness: %d\n", max_brightness); + printk(BIOS_INFO, "gmux brightness: %d\n", brightness); + + mode = HYBRID_GRAPHICS_DEFAULT_GPU; + get_option(&mode, "hybrid_graphics_mode"); + + gmux_switch(dev, mode == HYBRID_GRAPHICS_DISCRETE); +} + +struct chip_operations drivers_apple_hybrid_graphics_ops = { + CHIP_NAME("Apple hybrid graphics driver") + .enable_dev = enable_dev +}; diff --git a/src/drivers/apple/hybrid_graphics/hybrid_graphics.h b/src/drivers/apple/hybrid_graphics/hybrid_graphics.h new file mode 100644 index 0000000000..af2d56d528 --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/hybrid_graphics.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _DRIVERS_APPLE_HYBRID_GRAPHICS_H_ +#define _DRIVERS_APPLE_HYBRID_GRAPHICS_H_ + +#define HYBRID_GRAPHICS_PORT 0xff +#define HYBRID_GRAPHICS_DEVICE 0xf + +void early_hybrid_graphics(bool *enable_igd, bool *enable_peg); + +#endif /* _DRIVERS_APPLE_HYBRID_GRAPHICS_CHIP_H_ */ diff --git a/src/drivers/apple/hybrid_graphics/romstage.c b/src/drivers/apple/hybrid_graphics/romstage.c new file mode 100644 index 0000000000..8f2667111b --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/romstage.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> +#include <option.h> +#include <device/device.h> +#include <console/console.h> +#include "hybrid_graphics.h" +#include "chip.h" +#include "gmux.h" + +void early_hybrid_graphics(bool *enable_igd, bool *enable_peg) +{ + const struct device *dev; + enum hybrid_graphics_req mode = HYBRID_GRAPHICS_DEFAULT_GPU; + + /* TODO: Use generic device instead of dummy PNP device */ + dev = dev_find_slot_pnp(HYBRID_GRAPHICS_PORT, HYBRID_GRAPHICS_DEVICE); + + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "Hybrid graphics: ERROR\n"); + *enable_igd = true; + *enable_peg = false; + return; + } + + get_option(&mode, "hybrid_graphics_mode"); + + if (mode == HYBRID_GRAPHICS_DISCRETE) { + printk(BIOS_DEBUG, "Hybrid graphics:" + " Disabling integrated GPU.\n"); + + *enable_igd = false; + *enable_peg = true; + } else if (mode == HYBRID_GRAPHICS_INTEGRATED) { + printk(BIOS_DEBUG, "Hybrid graphics:" + " Disabling discrete GPU.\n"); + + *enable_igd = true; + *enable_peg = false; + } + + gmux_dgpu_power_enable(dev, *enable_peg); +} diff --git a/src/ec/apple/acpi/ac.asl b/src/ec/apple/acpi/ac.asl new file mode 100644 index 0000000000..0103229936 --- /dev/null +++ b/src/ec/apple/acpi/ac.asl @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope(\_SB.PCI0.LPCB.EC) +{ + Field(ERAM, ByteAcc, NoLock, Preserve) + { + Offset(HPAC_OFFSET), + , 1, + HPAC, 1, /* AC status */ + } + + Device(AC) + { + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_PSR, 0, NotSerialized) + { + Return(HPAC) + } + + Method(_STA, 0, NotSerialized) + { + Return(0x0f) + } + } +} diff --git a/src/ec/apple/acpi/battery.asl b/src/ec/apple/acpi/battery.asl new file mode 100644 index 0000000000..291451f414 --- /dev/null +++ b/src/ec/apple/acpi/battery.asl @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Field(ERAM, ByteAcc, NoLock, Preserve) +{ + Offset(0x20), + SPTR, 8, + SSTS, 8, + SADR, 8, + SCMD, 8, + SBFR, 256, +} + +Field(ERAM, ByteAcc, Lock, Preserve) +{ + Offset(0x24), + SBDW, 16, +} + +Method(SBPC, 0, NotSerialized) +{ + Local0 = 1000 + While (Local0) + { + If (SPTR == 0x00) + { + Return() + } + + Sleep(1) + Local0-- + } +} + +Method(SBRW, 2, NotSerialized) +{ + Acquire(ECLK, 0xFFFF) + SADR = ShiftLeft(Arg0, 0x01) + SCMD = Arg1 + SPTR = 0x09 + SBPC() + Local0 = SBDW + Release(ECLK) + Return(Local0) +} + +Method(SBRB, 2, NotSerialized) +{ + Acquire(ECLK, 0xFFFF) + SADR = ShiftLeft(Arg0, 0x01) + SCMD = Arg1 + SPTR = 0x0B + SBPC() + Local0 = SBFR + Release(ECLK) + Return(Local0) +} + +Device(BAT0) +{ + Name(_HID, EisaId("PNP0C0A")) + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB }) + + Name(BATS, Package() + { + 0x00, // 0: PowerUnit: Report in mWh + 0xFFFFFFFF, // 1: Design cap + 0xFFFFFFFF, // 2: Last full charge cap + 0x01, // 3: Battery Technology + 10800, // 4: Design Voltage(mV) + 0x00, // 5: Warning design capacity + 200, // 6: Low design capacity + 10, // 7: granularity1 + 10, // 8: granularity2 + "", // 9: Model number + "", // A: Serial number + "", // B: Battery Type + "" // C: OEM information + }) + + Name(BATI, Package() + { + 0, // Battery State + // Bit 0 - discharge + // Bit 1 - charge + // Bit 2 - critical state + 0, // Battery present Rate + 0, // Battery remaining capacity + 0 // Battery present voltage + }) + + Method(_BIF, 0, NotSerialized) + { + Index(BATS, 0x01) = ^^SBRW(0x0B, 0x18) * 10 + Index(BATS, 0x02) = ^^SBRW(0x0B, 0x10) * 10 + + Index(BATS, 0x04) = ^^SBRW(0x0B, 0x19) + Index(BATS, 0x09) = ^^SBRB(0x0B, 0x21) + Index(BATS, 0x0B) = ^^SBRB(0x0B, 0x22) + Index(BATS, 0x0C) = ^^SBRB(0x0B, 0x20) + + Return(BATS) + } + + Method(_STA, 0, NotSerialized) + { + If (^^SBRW(0x0A, 0x01) & 0x01) { + Return(0x1f) + } else { + Return(0x0f) + } + } + + Method(_BST, 0, NotSerialized) + { + /* Check for battery presence. */ + If (!(^^SBRW(0x0A, 0x01) & 0x01)) { + Return(Package(4) { + 0, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF + }) + } + + Local1 = ^^SBRW(0x0B, 0x09) + Index(BATI, 0x03) = Local1 + Local0 = ^^SBRW(0x0B, 0x0A) + + /* Sign-extend Local0. */ + If (Local0 & 0x8000) + { + Local0 = ~Local0 + Local0++ + Local0 &= 0xFFFF + } + + Local0 *= Local1 + Index(BATI, 1) = Local0 / 1000 + Index(BATI, 2) = ^^SBRW(0x0B, 0x0F) * 10 + If (HPAC) { + If (!(^^SBRW(0x0B, 0x16) & 0x40)) { + Index(BATI, 0) = 2 + } Else { + Index(BATI, 0) = 0 + } + } Else { + Index(BATI, 0) = 1 + } + + Return(BATI) + } +} diff --git a/src/ec/apple/acpi/ec.asl b/src/ec/apple/acpi/ec.asl new file mode 100644 index 0000000000..3adb7f6ab3 --- /dev/null +++ b/src/ec/apple/acpi/ec.asl @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device(EC) +{ + Name(_HID, EISAID("PNP0C09")) + Name(_UID, 0) + + Name(_GPE, 0x17) + Mutex(ECLK, 0) + + OperationRegion(ERAM, EmbeddedControl, 0x00, 0x100) + + /* LID status change. */ + Method(_Q20, 0, NotSerialized) + { + Notify(LID, 0x80) + } + + /* AC status change. */ + Method(_Q21, 0, NotSerialized) + { + Notify(AC, 0x80) + } + + Method(_CRS, 0) + { + Name(ECMD, ResourceTemplate() + { + IO(Decode16, 0x62, 0x62, 1, 1) + IO(Decode16, 0x66, 0x66, 1, 1) + }) + Return(ECMD) + } + + Method(_PRW, 0, NotSerialized) + { + Return(Package () { 0x23, 0x04 }) + } + + Method(_INI, 0, NotSerialized) + { + } + +#include "battery.asl" +} diff --git a/src/ec/apple/acpi/lid.asl b/src/ec/apple/acpi/lid.asl new file mode 100644 index 0000000000..ec91d8f106 --- /dev/null +++ b/src/ec/apple/acpi/lid.asl @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope(\_SB.PCI0.LPCB.EC) +{ + Field(ERAM, ByteAcc, NoLock, Preserve) + { + Offset(LIDS_OFFSET), + LIDS, 1, /* Lid status */ + + Offset(WKLD_OFFSET), + WKLD, 1, /* Lid wake */ + } + + Device(LID) + { + Name(_HID, "PNP0C0D") + + Method(_LID, 0, NotSerialized) + { + Return(LIDS) + } + + Method(_PRW, 0, NotSerialized) + { +#if LIDS_OFFSET == 0x01 + Return(Package() { 0x1d, 0x03 }) +#else + Return(Package() { 0x23, 0x04 }) +#endif + } + + Method(_PSW, 1, NotSerialized) + { + if (Arg0) { + WKLD = 1 + } else { + WKLD = 0 + } + } + } +} diff --git a/src/mainboard/apple/macbookpro10_1/Kconfig b/src/mainboard/apple/macbookpro10_1/Kconfig new file mode 100644 index 0000000000..4083660261 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Kconfig @@ -0,0 +1,48 @@ +if BOARD_APPLE_MACBOOKPRO10_1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_PANEL_1_ON_EDP + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select DRIVERS_APPLE_HYBRID_GRAPHICS + +config MAINBOARD_DIR + string + default apple/macbookpro10_1 + +config MAINBOARD_PART_NUMBER + string + default "MacBookPro10,1" + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" + +config DRAM_RESET_GATE_GPIO + int + default 28 + +config USBDEBUG_HCD_INDEX + int + default 0 + +config MAX_CPUS + int + default 8 +endif diff --git a/src/mainboard/apple/macbookpro10_1/Kconfig.name b/src/mainboard/apple/macbookpro10_1/Kconfig.name new file mode 100644 index 0000000000..c257f7a4fe --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_APPLE_MACBOOKPRO10_1 + bool "MacBookPro10,1" diff --git a/src/mainboard/apple/macbookpro10_1/Makefile.inc b/src/mainboard/apple/macbookpro10_1/Makefile.inc new file mode 100644 index 0000000000..143b4523c6 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Makefile.inc @@ -0,0 +1,11 @@ +romstage-y += gpio.c +romstage-y += early_init.c + +bootblock-y += gpio.c +bootblock-y += early_init.c + +cbfs-files-y += spd.bin +spd.bin-file := spd.bin +spd.bin-type := spd + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/apple/macbookpro10_1/acpi/ec.asl b/src/mainboard/apple/macbookpro10_1/acpi/ec.asl new file mode 100644 index 0000000000..9e61b4b988 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/ec.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define LIDS_OFFSET 0x60 +#define HPAC_OFFSET 0x60 +#define WKLD_OFFSET 0x68 + +#include <ec/apple/acpi/ec.asl> +#include <ec/apple/acpi/ac.asl> +#include <ec/apple/acpi/lid.asl> + +#include <drivers/apple/hybrid_graphics/acpi/gmux.asl> diff --git a/src/mainboard/apple/macbookpro10_1/acpi/platform.asl b/src/mainboard/apple/macbookpro10_1/acpi/platform.asl new file mode 100644 index 0000000000..a56d3190bd --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/apple/macbookpro10_1/acpi/superio.asl b/src/mainboard/apple/macbookpro10_1/acpi/superio.asl new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/superio.asl diff --git a/src/mainboard/apple/macbookpro10_1/acpi_tables.c b/src/mainboard/apple/macbookpro10_1/acpi_tables.c new file mode 100644 index 0000000000..ad1295b6b3 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi_tables.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <soc/nvs.h> + +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + /* The lid is open by default. */ + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/apple/macbookpro10_1/board_info.txt b/src/mainboard/apple/macbookpro10_1/board_info.txt new file mode 100644 index 0000000000..c916715bed --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: y +ROM package: SOIC-8 +ROM socketed: n +Release year: 2012 diff --git a/src/mainboard/apple/macbookpro10_1/cmos.default b/src/mainboard/apple/macbookpro10_1/cmos.default new file mode 100644 index 0000000000..efa97029f8 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/cmos.default @@ -0,0 +1,2 @@ +debug_level=Debug +hybrid_graphics_mode=Integrated Only diff --git a/src/mainboard/apple/macbookpro10_1/cmos.layout b/src/mainboard/apple/macbookpro10_1/cmos.layout new file mode 100644 index 0000000000..5e95eb23c0 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/cmos.layout @@ -0,0 +1,106 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: EC +#411 1 e 8 first_battery +#412 1 e 1 bluetooth +#413 1 e 1 wwan +#414 1 e 1 touchpad +#415 1 e 1 wlan +#416 1 e 1 trackpoint +#417 1 e 1 fn_ctrl_swap +#418 1 e 1 sticky_fn +#419 2 e 13 usb_always_on +#421 1 e 9 sata_mode +#422 2 e 10 backlight + +# coreboot config options: cpu +#424 8 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +435 2 e 12 hybrid_graphics_mode +#437 3 r 0 unused +#440 8 h 0 volume + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +12 0 Integrated Only +12 1 Discrete Only + +# ----------------------------------------------------------------- +checksums + +checksum 392 447 984 diff --git a/src/mainboard/apple/macbookpro10_1/devicetree.cb b/src/mainboard/apple/macbookpro10_1/devicetree.cb new file mode 100644 index 0000000000..3ab8739af9 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/devicetree.cb @@ -0,0 +1,85 @@ +chip northbridge/intel/sandybridge + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0x0000021c" + register "gpu_dp_b_hotplug" = "7" + register "gpu_dp_c_hotplug" = "7" + register "gpu_dp_d_hotplug" = "7" + register "gpu_panel_port_select" = "1" + register "gpu_panel_power_backlight_off_delay" = "2000" + register "gpu_panel_power_backlight_on_delay" = "2000" + register "gpu_panel_power_cycle_delay" = "5" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "600" + register "gpu_pch_backlight" = "0x021c0000" + + device cpu_cluster 0 on + chip cpu/intel/model_206ax + device lapic 0 on end + device lapic 0xacac off end + end + end + + device domain 0 on + subsystemid 0x8086 0x7270 inherit + device pci 00.0 on # Host bridge + subsystemid 0x106b 0x00f7 + end + device pci 01.0 on # PCIe Bridge for discrete graphics + subsystemid 0x106b 0x00f7 + end + device pci 01.2 on + subsystemid 0x106b 0x00f7 + end + device pci 01.1 on + subsystemid 0x106b 0x00f7 + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x106b 0x00f7 + end + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x001c0301" + register "gen4_dec" = "0x00fc0701" + register "gpi7_routing" = "2" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x08040201" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on end # USB 3.0 Controller + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # HD Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip drivers/apple/hybrid_graphics + device pnp ff.f on end # dummy + register "gmux_indexed" = "1" + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/apple/macbookpro10_1/dsdt.asl b/src/mainboard/apple/macbookpro10_1/dsdt.asl new file mode 100644 index 0000000000..fe72d28be0 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/apple/macbookpro10_1/early_init.c b/src/mainboard/apple/macbookpro10_1/early_init.c new file mode 100644 index 0000000000..25135b864d --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/early_init.c @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_ops.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <drivers/apple/hybrid_graphics/hybrid_graphics.h> +#include <cbfs.h> + +void mainboard_pch_lpc_setup(void) +{ + pci_write_config16(PCH_LPC_DEV, LPC_EN, 0x3f0f); + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x000c0681); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x000c1641); + pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x001c0301); + pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x00fc0701); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0070); +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, /* Ext A (XHCI/EHCI) */ + { 1, 0, 1 }, /* Ext B (XHCI) */ + { 1, 0, 2 }, /* Ext C (XHCI/EHCI) */ + { 1, 0, 3 }, /* Ext D (XHCI) */ + { 0, 0, -1 }, /* Unused */ + { 1, 0, -1 }, /* SD */ + { 1, 0, -1 }, /* Wi-Fi */ + { 1, 0, -1 }, /* USB Hub (All LS/FS Devices) */ + { 1, 0, -1 }, /* Camera */ + { 1, 0, 4 }, /* Ext B (EHCI) */ + { 1, 0, 5 }, /* Ext D (EHCI) */ + { 1, 0, -1 }, /* BT */ + { 0, 0, -1 }, /* Unused */ + { 0, 0, -1 }, /* Unused */ +}; + +void mainboard_early_init(int s3resume) +{ + bool igd, peg; + u32 reg32; + + early_hybrid_graphics(&igd, &peg); + + /* Hide disabled devices */ + reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); + + if (peg) + reg32 |= DEVEN_PEG10; + + if (igd) { + reg32 |= DEVEN_IGD; + } else { + /* Disable IGD VGA decode, no GTT or GFX stolen */ + pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); + } + + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + void *spd_file; + size_t spd_file_len = 0; + spd_file = cbfs_map("spd.bin", &spd_file_len); + + if (!spd_file || spd_file_len < 128) + die("Missing SPD data."); + + memcpy(&spd[0], spd_file, 128); + memcpy(&spd[2], spd_file, 128); +} diff --git a/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads b/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads new file mode 100644 index 0000000000..fd2a5d5bdb --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads @@ -0,0 +1,22 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/apple/macbookpro10_1/gpio.c b/src/mainboard/apple/macbookpro10_1/gpio.c new file mode 100644 index 0000000000..cec289e339 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/gpio.c @@ -0,0 +1,231 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio11 = GPIO_RESET_RSMRST, + .gpio15 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio67 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/apple/macbookpro10_1/hda_verb.c b/src/mainboard/apple/macbookpro10_1/hda_verb.c new file mode 100644 index 0000000000..cfdbcb7e8d --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/hda_verb.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10134206, /* Codec Vendor / Device ID: Cirrus CS4206 */ + 0x106b2800, /* Subsystem ID */ + + 11, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(0, 0x106b2800), + AZALIA_PIN_CFG(0, 0x09, 0x002b4020), + AZALIA_PIN_CFG(0, 0x0a, 0x90100112), + AZALIA_PIN_CFG(0, 0x0b, 0x90100110), + AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0d, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0e, 0x90a60100), + AZALIA_PIN_CFG(0, 0x0f, 0x400000f0), + AZALIA_PIN_CFG(0, 0x10, 0x004be030), + AZALIA_PIN_CFG(0, 0x12, 0x400000f0), + AZALIA_PIN_CFG(0, 0x15, 0x400000f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/apple/macbookpro10_1/mainboard.c b/src/mainboard/apple/macbookpro10_1/mainboard.c new file mode 100644 index 0000000000..75c58bfbe4 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/mainboard.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/apple/macbookpro10_1/spd.bin b/src/mainboard/apple/macbookpro10_1/spd.bin Binary files differnew file mode 100644 index 0000000000..2a0979deb7 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/spd.bin |
