diff options
| -rw-r--r-- | src/mainboard/amd/persimmon/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/amd/persimmon/OemCustomize.c | 14 | ||||
| -rw-r--r-- | src/mainboard/amd/persimmon/romstage.c | 83 |
3 files changed, 10 insertions, 88 deletions
diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index a61e3efec1..78c420345d 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -17,7 +17,6 @@ if BOARD_AMD_PERSIMMON config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select AGESA_LEGACY select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/persimmon/OemCustomize.c b/src/mainboard/amd/persimmon/OemCustomize.c index 825364ecbc..c0dceff5af 100644 --- a/src/mainboard/amd/persimmon/OemCustomize.c +++ b/src/mainboard/amd/persimmon/OemCustomize.c @@ -16,7 +16,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <PlatformMemoryConfiguration.h> @@ -36,7 +36,7 @@ * **/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; VOID *BrazosPcieComplexListPtr; @@ -132,7 +132,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -146,12 +145,13 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 6a4c12925f..f7dd9e5e8f 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -13,91 +13,14 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <commonlib/loglevel.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesa_helper.h> -#include <cpu/x86/bist.h> +#include <northbridge/amd/agesa/state_machine.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/cache.h> -#include <sb_cimx.h> -#include "SBPLATFORM.h" -#include "cbmem.h" -#include <cpu/amd/mtrr.h> -#include <cpu/amd/agesa/s3_resume.h> - #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - sb_Poweron_Init(); - - post_code(0x31); - fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - - post_code(0x42); - agesawrapper_amdinitenv(); - amd_initenv(); - - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } - - post_code(0x50); - copy_and_run(); - printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - - post_code(0x54); /* Should never see this post code. */ + fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } |