diff options
| -rw-r--r-- | src/arch/x86/bootblock_crt0.S | 2 | ||||
| -rw-r--r-- | src/arch/x86/gdt_init.S | 7 | ||||
| -rw-r--r-- | src/arch/x86/walkcbfs.S | 2 | ||||
| -rw-r--r-- | src/cpu/intel/car/core2/cache_as_ram.S | 1 | ||||
| -rw-r--r-- | src/cpu/intel/car/non-evict/cache_as_ram.S | 1 | ||||
| -rw-r--r-- | src/cpu/intel/car/p3/cache_as_ram.S | 1 | ||||
| -rw-r--r-- | src/cpu/intel/car/p4-netburst/cache_as_ram.S | 1 | ||||
| -rw-r--r-- | src/cpu/intel/microcode/microcode_asm.S | 2 | ||||
| -rw-r--r-- | src/cpu/qemu-x86/cache_as_ram_bootblock.S | 2 | ||||
| -rw-r--r-- | src/drivers/amd/agesa/cache_as_ram.S | 7 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/cache_as_ram.S | 2 | ||||
| -rw-r--r-- | src/lib/program.ld | 3 | ||||
| -rw-r--r-- | src/soc/amd/common/block/cpu/car/cache_as_ram.S | 11 | ||||
| -rw-r--r-- | src/soc/amd/common/block/cpu/noncar/pre_c.S | 2 | ||||
| -rw-r--r-- | src/soc/example/min86/cache_as_ram.S | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cpu/car/cache_as_ram.S | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S | 2 | ||||
| -rw-r--r-- | src/soc/intel/quark/bootblock/esram_init.S | 2 |
18 files changed, 44 insertions, 8 deletions
diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 82ae97f9c6..387920e38a 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -10,7 +10,7 @@ #include <cpu/x86/cr.h> -.section .text._start +.section .init._start, "ax", @progbits /* * Include the old code for reset vector and protected mode entry. That code has diff --git a/src/arch/x86/gdt_init.S b/src/arch/x86/gdt_init.S index 1558ac62c8..f33a1517d8 100644 --- a/src/arch/x86/gdt_init.S +++ b/src/arch/x86/gdt_init.S @@ -1,7 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ .code32 -.section ".text._gdt_", "ax", @progbits + +.section .init, "ax", @progbits + +.section .init._gdt_, "ax", @progbits .globl gdt_init gdt_init: @@ -17,7 +20,7 @@ gdtptr: #ifdef __x86_64__ .code64 -.section ".text._gdt64_", "ax", @progbits +.section .init._gdt64_, "ax", @progbits .globl gdt_init64 gdt_init64: /* Workaround a bug in the assembler. diff --git a/src/arch/x86/walkcbfs.S b/src/arch/x86/walkcbfs.S index b8d4fb985a..393bcf54ed 100644 --- a/src/arch/x86/walkcbfs.S +++ b/src/arch/x86/walkcbfs.S @@ -21,7 +21,7 @@ #define CBFS_FILE_STRUCTSIZE (CBFS_FILE_OFFSET + 4) .code32 -.section .text +.section .init .global walkcbfs_asm /* diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 837394c8c9..2c67207154 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -4,6 +4,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> +.section .init .global bootblock_pre_c_entry .code32 diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index cde1ca3d15..0451bb4dd5 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -7,6 +7,7 @@ #define NoEvictMod_MSR 0x2e0 #define BBL_CR_CTL3_MSR 0x11e +.section .init .global bootblock_pre_c_entry #include <cpu/intel/car/cache_as_ram_symbols.inc> diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 71e344778f..887bb22477 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -4,6 +4,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> +.section .init .global bootblock_pre_c_entry .code32 diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 4e36538414..103d9e97f9 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -8,6 +8,7 @@ /* Macro to access Local APIC registers at default base. */ #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) +.section .init .global bootblock_pre_c_entry .code32 diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S index 5173ae5a0c..28705230a2 100644 --- a/src/cpu/intel/microcode/microcode_asm.S +++ b/src/cpu/intel/microcode/microcode_asm.S @@ -44,7 +44,7 @@ */ .code32 -.section .text +.section .init .global update_bsp_microcode update_bsp_microcode: diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 197e0fd8e8..e3a26b0699 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -2,6 +2,8 @@ #include <cpu/x86/post_code.h> +.section .init, "ax", @progbits + .global bootblock_pre_c_entry bootblock_pre_c_entry: diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 8e7ea29b3c..33940cb489 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -10,16 +10,19 @@ ****************************************************************************** */ -#include "gcccar.inc" #include <cpu/x86/lapic_def.h> #include <cpu/x86/post_code.h> +.section .init + .code32 -.globl _cache_as_ram_setup, _cache_as_ram_setup_end + .global bootblock_pre_c_entry _cache_as_ram_setup: +#include "gcccar.inc" + /* * on entry: * mm0: BIST (ignored) diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index f1cfff771c..e20d5277ed 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -14,6 +14,8 @@ #define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ +.section .init, "ax", @progbits + .global bootblock_pre_c_entry bootblock_pre_c_entry: /* diff --git a/src/lib/program.ld b/src/lib/program.ld index d419ab60b1..3eebd6cc22 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -13,6 +13,9 @@ .text . : { _program = .; _text = .; + *(.init._start); + *(.init); + *(.init.*); *(.text._start); *(.text.stage_entry); KEEP(*(.metadata_hash_anchor)); diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S index 3eb7670784..6282d7e571 100644 --- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S @@ -8,9 +8,16 @@ ****************************************************************************** */ -#include "gcccar.inc" #include <cpu/x86/post_code.h> +.section .init + +.code32 + +_cache_as_ram_setup: + +#include "gcccar.inc" + /* * on entry: * mm0: BIST (ignored) @@ -43,3 +50,5 @@ before_carstage: post_code(POST_DEAD_CODE) hlt jmp .halt_forever + +_cache_as_ram_setup_end: diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S index 6fae1ed1cb..520e3c08b0 100644 --- a/src/soc/amd/common/block/cpu/noncar/pre_c.S +++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S @@ -2,6 +2,8 @@ #include <cpu/x86/post_code.h> +.section .init, "ax", @progbits + .global bootblock_resume_entry bootblock_resume_entry: post_code(0xb0) diff --git a/src/soc/example/min86/cache_as_ram.S b/src/soc/example/min86/cache_as_ram.S index a350143834..5c5066d7ea 100644 --- a/src/soc/example/min86/cache_as_ram.S +++ b/src/soc/example/min86/cache_as_ram.S @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +.section .init, "ax", @progbits + .global bootblock_pre_c_entry .code32 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index aaf6af7d5a..49b40a8d9a 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -9,6 +9,8 @@ #include <rules.h> #include <intelblocks/msr.h> +.section .init, "ax", @progbits + .code32 .global bootblock_pre_c_entry bootblock_pre_c_entry: diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 04dc5331e1..a2e85b9aac 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -10,6 +10,8 @@ #define CBFS_FILE_CHECKSUM (CBFS_FILE_TYPE + 4) #define CBFS_FILE_OFFSET (CBFS_FILE_CHECKSUM + 4) +.section .init, "ax", @progbits + .extern temp_ram_init_params .global bootblock_pre_c_entry diff --git a/src/soc/intel/quark/bootblock/esram_init.S b/src/soc/intel/quark/bootblock/esram_init.S index fc1c7c903f..39ce7bd02d 100644 --- a/src/soc/intel/quark/bootblock/esram_init.S +++ b/src/soc/intel/quark/bootblock/esram_init.S @@ -71,6 +71,8 @@ .equ CFGNONSTICKY_W1_OFFSET, (0x52) .equ FORCE_WARM_RESET, (0x00000001) +.section .init, "ax", @progbits + .global bootblock_pre_c_entry bootblock_pre_c_entry: |