21 files changed, 30 insertions, 78 deletions

diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c
index b1ae27dbe9..c60fbaaaad 100644
--- a/src/drivers/usb/ehci_debug.c
+++ b/src/drivers/usb/ehci_debug.c
@@ -569,6 +569,8 @@ static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_
 	int port_map_tried;
 	int playtimes = 3;
 
+	dprintk(BIOS_INFO, "ehci_bar: 0x%x debug_offset 0x%x\n", ehci_bar, offset);
+
 	ehci_caps  = (struct ehci_caps *)ehci_bar;
 	ehci_regs  = (struct ehci_regs *)(ehci_bar +
 			HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase)));
@@ -589,7 +591,6 @@ try_next_port:
 	debug_port = HCS_DEBUG_PORT(hcs_params);
 	n_ports    = HCS_N_PORTS(hcs_params);
 
-	dprintk(BIOS_INFO, "ehci_bar: 0x%x\n", ehci_bar);
 	dprintk(BIOS_INFO, "debug_port: %d\n", debug_port);
 	dprintk(BIOS_INFO, "n_ports:    %d\n", n_ports);
 
@@ -926,11 +927,13 @@ struct dbgp_pipe *dbgp_console_input(void)
 int usbdebug_init(void)
 {
 	struct ehci_debug_info *dbg_info = dbgp_ehci_info();
+	unsigned int ehci_base, dbg_offset;
 
 #if !defined(__PRE_RAM__) && !defined(__SMM__)
 	if (!get_usbdebug_from_cbmem(dbg_info))
 		return 0;
 #endif
-	ehci_debug_hw_enable();
-	return usbdebug_init_(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info);
+	if (ehci_debug_hw_enable(&ehci_base, &dbg_offset))
+		return -1;
+	return usbdebug_init_(ehci_base, dbg_offset, dbg_info);
 }
diff --git a/src/drivers/usb/ehci_debug.h b/src/drivers/usb/ehci_debug.h
index 7cfac011e1..30bf724cb8 100644
--- a/src/drivers/usb/ehci_debug.h
+++ b/src/drivers/usb/ehci_debug.h
@@ -24,10 +24,12 @@
 void usbdebug_re_enable(unsigned ehci_base);
 void usbdebug_disable(void);
 
-void ehci_debug_hw_enable(void);
+/* Returns 0 on success and sets MMIO base and dbg_offset if EHCI debug
+ * capability was found and enabled. Returns non-zero on error.
+ */
+int ehci_debug_hw_enable(unsigned *base, unsigned *dbg_offset);
 void ehci_debug_select_port(unsigned int port);
 
-
 #define DBGP_EP_VALID		(1<<0)
 #define DBGP_EP_ENABLED		(1<<1)
 #define DBGP_EP_BUSY		(1<<2)
diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c
index 7c715f67bd..c7e8afb06f 100644
--- a/src/drivers/usb/pci_ehci.c
+++ b/src/drivers/usb/pci_ehci.c
@@ -34,12 +34,30 @@ static struct device_operations *ehci_drv_ops;
 static struct device_operations ehci_dbg_ops;
 #endif
 
-void ehci_debug_hw_enable(void)
+int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset)
 {
-#if defined(__PRE_RAM__) || !CONFIG_USBDEBUG_IN_ROMSTAGE
 	pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
 	pci_ehci_dbg_enable(dbg_dev, CONFIG_EHCI_BAR);
+#ifdef __SIMPLE_DEVICE__
+	pci_devfn_t dev = dbg_dev;
+#else
+	device_t dev = dev_find_slot(PCI_DEV2SEGBUS(dbg_dev), PCI_DEV2DEVFN(dbg_dev));
 #endif
+
+	u8 pos = pci_find_capability(dev, PCI_CAP_ID_EHCI_DEBUG);
+	if (!pos)
+		return -1;
+
+	u32 cap = pci_read_config32(dev, pos);
+
+	/* FIXME: We should remove static EHCI_BAR_INDEX. */
+	u8 dbg_bar = 0x10 + 4 * ((cap >> 29) - 1);
+	if (dbg_bar != EHCI_BAR_INDEX)
+		return -1;
+
+	*base = CONFIG_EHCI_BAR;
+	*dbg_offset = (cap>>16) & 0x1ffc;
+	return 0;
 }
 
 void ehci_debug_select_port(unsigned int port)
diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig
index 1550cb4c01..dd5120dbf7 100644
--- a/src/southbridge/amd/agesa/hudson/Kconfig
+++ b/src/southbridge/amd/agesa/hudson/Kconfig
@@ -43,10 +43,6 @@ config EHCI_BAR
 	hex
 	default 0xfef00000
 
-config EHCI_DEBUG_OFFSET
-	hex
-	default 0xe0
-
 config HUDSON_XHCI_ENABLE
 	bool "Enable Hudson XHCI Controller"
 	default y
diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig
index 4304357a7a..d8bad86007 100644
--- a/src/southbridge/amd/cimx/sb700/Kconfig
+++ b/src/southbridge/amd/cimx/sb700/Kconfig
@@ -54,10 +54,6 @@ config EHCI_BAR
 	hex
 	default 0xfef00000
 
-config EHCI_DEBUG_OFFSET
-	hex
-	default 0xe0
-
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
 	default "southbridge/amd/cimx/sb700/bootblock.c"
diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index 37aff9ef45..832655d16d 100644
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -209,10 +209,6 @@ config EHCI_BAR
 	hex
 	default 0xfef00000
 
-config EHCI_DEBUG_OFFSET
-	hex
-	default 0xe0
-
 choice
 	prompt "Fan Control"
 	default SB800_NO_FAN_CONTROL
diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig
index fe9468d4af..4d5fff49fd 100644
--- a/src/southbridge/amd/sb600/Kconfig
+++ b/src/southbridge/amd/sb600/Kconfig
@@ -32,10 +32,6 @@ config EHCI_BAR
 	hex
 	default 0xfef00000
 
-config EHCI_DEBUG_OFFSET
-	hex
-	default 0xe0
-
 choice
 	prompt "SATA Mode"
 	default SATA_MODE_IDE
diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig
index b0c92dcedb..e391fc8928 100644
--- a/src/southbridge/amd/sb700/Kconfig
+++ b/src/southbridge/amd/sb700/Kconfig
@@ -45,8 +45,4 @@ config EHCI_BAR
 	hex
 	default 0xfef00000
 
-config EHCI_DEBUG_OFFSET
-	hex
-	default 0xe0
-
 endif # SOUTHBRIDGE_AMD_SB700
diff --git a/src/southbridge/amd/sb800/Kconfig b/src/southbridge/amd/sb800/Kconfig
index 9547d3e7c8..24dc007404 100644
--- a/src/southbridge/amd/sb800/Kconfig
+++ b/src/southbridge/amd/sb800/Kconfig
@@ -37,8 +37,4 @@ config EHCI_BAR
 	hex
 	default 0xfef00000
 
-config EHCI_DEBUG_OFFSET
-	hex
-	default 0xe0
-
 endif # SOUTHBRIDGE_AMD_SB800
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index d060dae406..9cfa5d5b26 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -41,10 +41,6 @@ config EHCI_BAR
 	hex
 	default 0xfef00000
 
-config EHCI_DEBUG_OFFSET
-	hex
-	default 0xa0
-
 config DRAM_RESET_GATE_GPIO
 	int
 	default 60
diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig
index 1a8e80ac07..b2b4929348 100644
--- a/src/southbridge/intel/fsp_bd82x6x/Kconfig
+++ b/src/southbridge/intel/fsp_bd82x6x/Kconfig
@@ -37,10 +37,6 @@ config EHCI_BAR
 	hex
 	default 0xfef00000
 
-config EHCI_DEBUG_OFFSET
-	hex
-	default 0xa0
-
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
 	default "southbridge/intel/fsp_bd82x6x/bootblock.c"
diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig
index f7f93a7c78..8ef778fad3 100644
--- a/src/southbridge/intel/i82801dx/Kconfig
+++ b/src/southbridge/intel/i82801dx/Kconfig
@@ -33,8 +33,4 @@ config EHCI_BAR
 	hex
 	default 0xfef00000
 
-config EHCI_DEBUG_OFFSET
-	hex
-	default 0x80
-
 endif
diff --git a/src/southbridge/intel/i82801ex/Kconfig b/src/southbridge/intel/i82801ex/Kconfig
index e4e9160a41..caa5c79ad9 100644
--- a/src/southbridge/intel/i82801ex/Kconfig
+++ b/src/southbridge/intel/i82801ex/Kconfig
@@ -11,8 +11,4 @@ config EHCI_BAR
 	hex
 	default 0xfef00000
 
-config EHCI_DEBUG_OFFSET
-	hex
-	default 0xa0
-
 endif
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index 62c6b436f2..777b69b600 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -32,10 +32,6 @@ config EHCI_BAR
 	hex
 	default 0xfef00000
 
-config EHCI_DEBUG_OFFSET
-	hex
-	default 0xa0
-
 config BOOTBLOCK_SOUTHBRIDGE_INIT
         string
 	default "southbridge/intel/i82801gx/bootblock.c"
diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig
index 8a4a53ef78..493be60123 100644
--- a/src/southbridge/intel/i82801ix/Kconfig
+++ b/src/southbridge/intel/i82801ix/Kconfig
@@ -33,10 +33,6 @@ config EHCI_BAR
 	hex
 	default 0xfef00000
 
-config EHCI_DEBUG_OFFSET
-	hex
-	default 0xa0
-
 config BOOTBLOCK_SOUTHBRIDGE_INIT
         string
 	default "southbridge/intel/i82801ix/bootblock.c"
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index 97d5883222..c05fe43475 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -39,10 +39,6 @@ config EHCI_BAR
 	hex
 	default 0xfef00000
 
-config EHCI_DEBUG_OFFSET
-	hex
-	default 0xa0
-
 config DRAM_RESET_GATE_GPIO
 	int
 	default 60
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index 5ff00db1e6..bfb7b734cb 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -44,10 +44,6 @@ config EHCI_BAR
 	hex
 	default 0xe8000000
 
-config EHCI_DEBUG_OFFSET
-	hex
-	default 0xa0
-
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
 	default "southbridge/intel/lynxpoint/bootblock.c"
diff --git a/src/southbridge/intel/sch/Kconfig b/src/southbridge/intel/sch/Kconfig
index 432fb8d566..d320a53332 100644
--- a/src/southbridge/intel/sch/Kconfig
+++ b/src/southbridge/intel/sch/Kconfig
@@ -30,10 +30,6 @@ config EHCI_BAR
 	hex
 	default 0xfef00000
 
-config EHCI_DEBUG_OFFSET
-	hex
-	default 0xa0
-
 config HAVE_CMC
 	bool "Add a CMC state machine binary"
 	help
diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig
index b6f718ee1b..e21f79e655 100644
--- a/src/southbridge/nvidia/ck804/Kconfig
+++ b/src/southbridge/nvidia/ck804/Kconfig
@@ -14,10 +14,6 @@ config EHCI_BAR
 	hex
 	default 0xfef00000
 
-config EHCI_DEBUG_OFFSET
-	hex
-	default 0x98
-
 config CK804_USE_NIC
 	bool
 	default n
diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig
index cd6009de67..89aa45258a 100644
--- a/src/southbridge/nvidia/mcp55/Kconfig
+++ b/src/southbridge/nvidia/mcp55/Kconfig
@@ -14,10 +14,6 @@ config EHCI_BAR
 	hex
 	default 0xfef00000
 
-config EHCI_DEBUG_OFFSET
-	hex
-	default 0x98
-
 config MCP55_USE_NIC
 	bool
 	default n
diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig
index 03dd6b1fd6..1fbd57d7dc 100644
--- a/src/southbridge/sis/sis966/Kconfig
+++ b/src/southbridge/sis/sis966/Kconfig
@@ -12,6 +12,3 @@ config EHCI_BAR
 	hex
 	default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966
 
-config EHCI_DEBUG_OFFSET
-	hex
-	default 0x98 if SOUTHBRIDGE_SIS_SIS966