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-rw-r--r--src/device/azalia_device.c10
-rw-r--r--src/include/device/azalia_device.h1
-rw-r--r--src/soc/intel/common/Kconfig.common1
-rw-r--r--src/soc/intel/common/hda_verb.c35
-rw-r--r--src/southbridge/intel/bd82x6x/Kconfig1
-rw-r--r--src/southbridge/intel/bd82x6x/azalia.c31
-rw-r--r--src/southbridge/intel/i82801gx/Kconfig1
-rw-r--r--src/southbridge/intel/i82801gx/azalia.c33
-rw-r--r--src/southbridge/intel/i82801ix/Kconfig1
-rw-r--r--src/southbridge/intel/i82801ix/azalia.c33
-rw-r--r--src/southbridge/intel/i82801jx/Kconfig1
-rw-r--r--src/southbridge/intel/i82801jx/azalia.c33
-rw-r--r--src/southbridge/intel/ibexpeak/Kconfig1
-rw-r--r--src/southbridge/intel/ibexpeak/azalia.c31
-rw-r--r--src/southbridge/intel/lynxpoint/Kconfig1
-rw-r--r--src/southbridge/intel/lynxpoint/hda_verb.c31
16 files changed, 32 insertions, 213 deletions
diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c
index 4ab45bcc09..543d5cb3ea 100644
--- a/src/device/azalia_device.c
+++ b/src/device/azalia_device.c
@@ -7,7 +7,7 @@
#include <device/mmio.h>
#include <delay.h>
-static int set_bits(void *port, u32 mask, u32 val)
+int azalia_set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -40,7 +40,7 @@ static int codec_detect(u8 *base)
int count;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
- if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0)
+ if (azalia_set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0)
goto no_codec;
/* clear STATESTS bits (BAR + 0xe)[2:0] */
@@ -62,11 +62,11 @@ static int codec_detect(u8 *base)
goto no_codec;
/* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */
- if (set_bits(base + HDA_GCTL_REG, 1, 0) < 0)
+ if (azalia_set_bits(base + HDA_GCTL_REG, 1, 0) < 0)
goto no_codec;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
- if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0)
+ if (azalia_set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0)
goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0] */
@@ -80,7 +80,7 @@ static int codec_detect(u8 *base)
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
- set_bits(base + HDA_GCTL_REG, 1, 0);
+ azalia_set_bits(base + HDA_GCTL_REG, 1, 0);
printk(BIOS_DEBUG, "azalia_audio: No codec!\n");
return 0;
}
diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h
index d682772e26..7bb8e10fbc 100644
--- a/src/include/device/azalia_device.h
+++ b/src/include/device/azalia_device.h
@@ -18,6 +18,7 @@
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
+int azalia_set_bits(void *port, u32 mask, u32 val);
void azalia_audio_init(struct device *dev);
extern struct device_operations default_azalia_audio_ops;
diff --git a/src/soc/intel/common/Kconfig.common b/src/soc/intel/common/Kconfig.common
index ba0b2db32f..1a59d04087 100644
--- a/src/soc/intel/common/Kconfig.common
+++ b/src/soc/intel/common/Kconfig.common
@@ -1,5 +1,6 @@
config SOC_INTEL_COMMON
bool
+ select AZALIA_PLUGIN_SUPPORT
select HAVE_DISPLAY_MTRRS
help
common code for Intel SOCs
diff --git a/src/soc/intel/common/hda_verb.c b/src/soc/intel/common/hda_verb.c
index 83bbb59588..57104c494e 100644
--- a/src/soc/intel/common/hda_verb.c
+++ b/src/soc/intel/common/hda_verb.c
@@ -7,39 +7,12 @@
#include "hda_verb.h"
-static int set_bits(void *port, u32 mask, u32 val)
-{
- u32 reg32;
- int count;
-
- /* Write (val & mask) to port */
- val &= mask;
- reg32 = read32(port);
- reg32 &= ~mask;
- reg32 |= val;
- write32(port, reg32);
-
- /* Wait for readback of register to match what was just written to it */
- count = 50;
- do {
- /* Wait 1ms based on BKDG wait time */
- mdelay(1);
- reg32 = read32(port);
- reg32 &= mask;
- } while ((reg32 != val) && --count);
-
- /* Timeout occurred */
- if (!count)
- return -1;
- return 0;
-}
-
int hda_codec_detect(u8 *base)
{
u8 reg8;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
- if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
+ if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
goto no_codec;
/* Write back the value once reset bit is set. */
@@ -51,11 +24,11 @@ int hda_codec_detect(u8 *base)
write8(base + HDA_STATESTS_REG, 0xf);
/* Turn off the link and poll RESET# bit until it reads back as 0 */
- if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, ~HDA_GCTL_CRST) < 0)
+ if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, ~HDA_GCTL_CRST) < 0)
goto no_codec;
/* Turn on the link and poll RESET# bit until it reads back as 1 */
- if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
+ if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0]*/
@@ -69,7 +42,7 @@ int hda_codec_detect(u8 *base)
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
- set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0);
+ azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0);
printk(BIOS_DEBUG, "HDA: No codec!\n");
return 0;
}
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index 7852ace972..3b05a3e678 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -11,6 +11,7 @@ if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216
config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
+ select AZALIA_PLUGIN_SUPPORT
select SOUTHBRIDGE_INTEL_COMMON_FINALIZE
select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index 972b2531e2..5e810c4cc0 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -14,39 +14,12 @@
typedef struct southbridge_intel_bd82x6x_config config_t;
-static int set_bits(void *port, u32 mask, u32 val)
-{
- u32 reg32;
- int count;
-
- /* Write (val & mask) to port */
- val &= mask;
- reg32 = read32(port);
- reg32 &= ~mask;
- reg32 |= val;
- write32(port, reg32);
-
- /* Wait for readback of register to match what was just written to it */
- count = 50;
- do {
- /* Wait 1ms based on BKDG wait time */
- mdelay(1);
- reg32 = read32(port);
- reg32 &= mask;
- } while ((reg32 != val) && --count);
-
- /* Timeout occurred */
- if (!count)
- return -1;
- return 0;
-}
-
static int codec_detect(u8 *base)
{
u8 reg8;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
- if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
+ if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
goto no_codec;
/* Write back the value once reset bit is set. */
@@ -63,7 +36,7 @@ static int codec_detect(u8 *base)
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
- set_bits(base + HDA_GCTL_REG, 1, 0);
+ azalia_set_bits(base + HDA_GCTL_REG, 1, 0);
printk(BIOS_DEBUG, "Azalia: No codec!\n");
return 0;
}
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index 50f7c6093c..2d3bf24b3e 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -3,6 +3,7 @@
config SOUTHBRIDGE_INTEL_I82801GX
bool
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
+ select AZALIA_PLUGIN_SUPPORT
select IOAPIC
select USE_WATCHDOG_ON_BOOT
select HAVE_SMI_HANDLER
diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c
index 1927adc749..a511468171 100644
--- a/src/southbridge/intel/i82801gx/azalia.c
+++ b/src/southbridge/intel/i82801gx/azalia.c
@@ -11,43 +11,16 @@
#include "chip.h"
#include "i82801gx.h"
-static int set_bits(void *port, u32 mask, u32 val)
-{
- u32 reg32;
- int count;
-
- /* Write (val & mask) to port */
- val &= mask;
- reg32 = read32(port);
- reg32 &= ~mask;
- reg32 |= val;
- write32(port, reg32);
-
- /* Wait for readback of register to match what was just written to it */
- count = 50;
- do {
- /* Wait 1ms based on BKDG wait time */
- mdelay(1);
- reg32 = read32(port);
- reg32 &= mask;
- } while ((reg32 != val) && --count);
-
- /* Timeout occurred */
- if (!count)
- return -1;
- return 0;
-}
-
static int codec_detect(u8 *base)
{
u32 reg32;
/* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */
- if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0)
+ if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0)
goto no_codec;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
- if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
+ if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0] */
@@ -61,7 +34,7 @@ static int codec_detect(u8 *base)
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
- set_bits(base + HDA_GCTL_REG, 1, 0);
+ azalia_set_bits(base + HDA_GCTL_REG, 1, 0);
printk(BIOS_DEBUG, "Azalia: No codec!\n");
return 0;
}
diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig
index 11a6d39938..be640db0c3 100644
--- a/src/southbridge/intel/i82801ix/Kconfig
+++ b/src/southbridge/intel/i82801ix/Kconfig
@@ -3,6 +3,7 @@
config SOUTHBRIDGE_INTEL_I82801IX
bool
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
+ select AZALIA_PLUGIN_SUPPORT
select HAVE_SMI_HANDLER if !NO_SMM
select HAVE_USBDEBUG_OPTIONS
select INTEL_DESCRIPTOR_MODE_CAPABLE
diff --git a/src/southbridge/intel/i82801ix/azalia.c b/src/southbridge/intel/i82801ix/azalia.c
index d6c75339a8..7078e6798b 100644
--- a/src/southbridge/intel/i82801ix/azalia.c
+++ b/src/southbridge/intel/i82801ix/azalia.c
@@ -11,43 +11,16 @@
#include "chip.h"
#include "i82801ix.h"
-static int set_bits(void *port, u32 mask, u32 val)
-{
- u32 reg32;
- int count;
-
- /* Write (val & mask) to port */
- val &= mask;
- reg32 = read32(port);
- reg32 &= ~mask;
- reg32 |= val;
- write32(port, reg32);
-
- /* Wait for readback of register to match what was just written to it */
- count = 50;
- do {
- /* Wait 1ms based on BKDG wait time */
- mdelay(1);
- reg32 = read32(port);
- reg32 &= mask;
- } while ((reg32 != val) && --count);
-
- /* Timeout occurred */
- if (!count)
- return -1;
- return 0;
-}
-
static int codec_detect(u8 *base)
{
u32 reg32;
/* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */
- if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0)
+ if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0)
goto no_codec;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
- if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
+ if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0] */
@@ -61,7 +34,7 @@ static int codec_detect(u8 *base)
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
- set_bits(base + HDA_GCTL_REG, 1, 0);
+ azalia_set_bits(base + HDA_GCTL_REG, 1, 0);
printk(BIOS_DEBUG, "Azalia: No codec!\n");
return 0;
}
diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig
index 6abeac1f49..687cb45924 100644
--- a/src/southbridge/intel/i82801jx/Kconfig
+++ b/src/southbridge/intel/i82801jx/Kconfig
@@ -3,6 +3,7 @@
config SOUTHBRIDGE_INTEL_I82801JX
bool
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
+ select AZALIA_PLUGIN_SUPPORT
select HAVE_POWER_STATE_AFTER_FAILURE
select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
select HAVE_SMI_HANDLER
diff --git a/src/southbridge/intel/i82801jx/azalia.c b/src/southbridge/intel/i82801jx/azalia.c
index bf41490a00..982efb7412 100644
--- a/src/southbridge/intel/i82801jx/azalia.c
+++ b/src/southbridge/intel/i82801jx/azalia.c
@@ -11,43 +11,16 @@
#include "chip.h"
#include "i82801jx.h"
-static int set_bits(void *port, u32 mask, u32 val)
-{
- u32 reg32;
- int count;
-
- /* Write (val & mask) to port */
- val &= mask;
- reg32 = read32(port);
- reg32 &= ~mask;
- reg32 |= val;
- write32(port, reg32);
-
- /* Wait for readback of register to match what was just written to it */
- count = 50;
- do {
- /* Wait 1ms based on BKDG wait time */
- mdelay(1);
- reg32 = read32(port);
- reg32 &= mask;
- } while ((reg32 != val) && --count);
-
- /* Timeout occurred */
- if (!count)
- return -1;
- return 0;
-}
-
static int codec_detect(u8 *base)
{
u32 reg32;
/* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */
- if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0)
+ if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0)
goto no_codec;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
- if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
+ if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0] */
@@ -61,7 +34,7 @@ static int codec_detect(u8 *base)
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
- set_bits(base + HDA_GCTL_REG, 1, 0);
+ azalia_set_bits(base + HDA_GCTL_REG, 1, 0);
printk(BIOS_DEBUG, "Azalia: No codec!\n");
return 0;
}
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index 07f9b6b110..c54c7e4d6c 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -8,6 +8,7 @@ if SOUTHBRIDGE_INTEL_IBEXPEAK
config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
+ select AZALIA_PLUGIN_SUPPORT
select IOAPIC
select HAVE_SMI_HANDLER
select USE_WATCHDOG_ON_BOOT
diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c
index 97e705e287..0c19598aa3 100644
--- a/src/southbridge/intel/ibexpeak/azalia.c
+++ b/src/southbridge/intel/ibexpeak/azalia.c
@@ -10,39 +10,12 @@
#include <device/azalia_device.h>
#include "pch.h"
-static int set_bits(void *port, u32 mask, u32 val)
-{
- u32 reg32;
- int count;
-
- /* Write (val & mask) to port */
- val &= mask;
- reg32 = read32(port);
- reg32 &= ~mask;
- reg32 |= val;
- write32(port, reg32);
-
- /* Wait for readback of register to match what was just written to it */
- count = 50;
- do {
- /* Wait 1ms based on BKDG wait time */
- mdelay(1);
- reg32 = read32(port);
- reg32 &= mask;
- } while ((reg32 != val) && --count);
-
- /* Timeout occurred */
- if (!count)
- return -1;
- return 0;
-}
-
static int codec_detect(u8 *base)
{
u8 reg8;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
- if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
+ if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
goto no_codec;
/* Write back the value once reset bit is set. */
@@ -59,7 +32,7 @@ static int codec_detect(u8 *base)
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
- set_bits(base + HDA_GCTL_REG, 1, 0);
+ azalia_set_bits(base + HDA_GCTL_REG, 1, 0);
printk(BIOS_DEBUG, "Azalia: No codec!\n");
return 0;
}
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index 7ba86b8fcc..a88a9a8bc2 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -8,6 +8,7 @@ if SOUTHBRIDGE_INTEL_LYNXPOINT
config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
+ select AZALIA_PLUGIN_SUPPORT
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c
index 24897cab91..7c6537d003 100644
--- a/src/southbridge/intel/lynxpoint/hda_verb.c
+++ b/src/southbridge/intel/lynxpoint/hda_verb.c
@@ -8,39 +8,12 @@
#include "pch.h"
#include "hda_verb.h"
-static int set_bits(void *port, u32 mask, u32 val)
-{
- u32 reg32;
- int count;
-
- /* Write (val & mask) to port */
- val &= mask;
- reg32 = read32(port);
- reg32 &= ~mask;
- reg32 |= val;
- write32(port, reg32);
-
- /* Wait for readback of register to match what was just written to it */
- count = 50;
- do {
- /* Wait 1ms based on BKDG wait time */
- mdelay(1);
- reg32 = read32(port);
- reg32 &= mask;
- } while ((reg32 != val) && --count);
-
- /* Timeout occurred */
- if (!count)
- return -1;
- return 0;
-}
-
int hda_codec_detect(u8 *base)
{
u8 reg8;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
- if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
+ if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
goto no_codec;
/* Write back the value once reset bit is set. */
@@ -57,7 +30,7 @@ int hda_codec_detect(u8 *base)
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
- set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0);
+ azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0);
printk(BIOS_DEBUG, "HDA: No codec!\n");
return 0;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 22:12:23 +0000