diff options
| -rw-r--r-- | src/soc/intel/tigerlake/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params_jsl.c (renamed from src/soc/intel/tigerlake/fsp_params.c) | 0 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params_tgl.c | 46 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params_jsl.c (renamed from src/soc/intel/tigerlake/romstage/fsp_params.c) | 0 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params_tgl.c | 22 |
6 files changed, 72 insertions, 2 deletions
diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 0d5aecb328..532861dbe1 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -33,7 +33,8 @@ ramstage-y += cpu.c ramstage-y += elog.c ramstage-y += espi.c ramstage-y += finalize.c -ramstage-y += fsp_params.c +ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += fsp_params_tgl.c +ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += fsp_params_jsl.c ramstage-y += gpio.c ramstage-y += graphics.c ramstage-y += lockdown.c diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params_jsl.c index 6fb2f9f597..6fb2f9f597 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params_jsl.c diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c new file mode 100644 index 0000000000..6fb2f9f597 --- /dev/null +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/api.h> +#include <intelblocks/lpss.h> +#include <soc/ramstage.h> + +static const pci_devfn_t serial_io_dev[] = { + PCH_DEVFN_I2C0, + PCH_DEVFN_I2C1, + PCH_DEVFN_I2C2, + PCH_DEVFN_I2C3, + PCH_DEVFN_I2C4, + PCH_DEVFN_I2C5, + PCH_DEVFN_GSPI0, + PCH_DEVFN_GSPI1, + PCH_DEVFN_GSPI2, + PCH_DEVFN_UART0, + PCH_DEVFN_UART1, + PCH_DEVFN_UART2 +}; + +/* UPD parameters to be initialized before SiliconInit */ +void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) +{ + /* TODO: Update with UPD override as FSP matures */ +} + +/* Return list of SOC LPSS controllers */ +const pci_devfn_t *soc_lpss_controllers_list(size_t *size) +{ + *size = ARRAY_SIZE(serial_io_dev); + return serial_io_dev; +} diff --git a/src/soc/intel/tigerlake/romstage/Makefile.inc b/src/soc/intel/tigerlake/romstage/Makefile.inc index 8d151e3871..2bf9812c08 100644 --- a/src/soc/intel/tigerlake/romstage/Makefile.inc +++ b/src/soc/intel/tigerlake/romstage/Makefile.inc @@ -13,7 +13,8 @@ # GNU General Public License for more details. # -romstage-y += fsp_params.c +romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += fsp_params_tgl.c +romstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += fsp_params_jsl.c romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += pch.c diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c index 810cff4a20..810cff4a20 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c new file mode 100644 index 0000000000..810cff4a20 --- /dev/null +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/util.h> +#include <soc/romstage.h> + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ + /* TODO: Update with UPD override as FSP matures */ +} |