diff options
| -rw-r--r-- | src/cpu/x86/smm/smmrelocate.S | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/Kconfig | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/northbridge.c | 51 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/ram_calc.c | 47 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/x4x.h | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/Makefile.inc | 2 |
6 files changed, 76 insertions, 29 deletions
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 16bccbce45..bd12581a76 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -27,9 +27,6 @@ #include <southbridge/intel/i82801dx/i82801dx.h> #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801IX) #include <southbridge/intel/i82801ix/i82801ix.h> -#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801JX) -#include <southbridge/intel/i82801jx/i82801jx.h> - #else #error "Southbridge needs SMM handler support." #endif diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 1c65614d9d..117ac03882 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -28,6 +28,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select CACHE_MRC_SETTINGS select POSTCAR_STAGE select POSTCAR_CONSOLE + select SMM_TSEG config CBFS_SIZE hex diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index bc7a5b39ae..d6094ac3da 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -29,14 +29,15 @@ #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/chip.h> #include <northbridge/intel/x4x/x4x.h> +#include <cpu/intel/smm/gen1/smi.h> static const int legacy_hole_base_k = 0xa0000 / 1024; static void mch_domain_read_resources(struct device *dev) { - u8 index, reg8; + u8 index; u64 tom, touud; - u32 tomk, tseg_sizek = 0, tolud, delta_cbmem; + u32 tomk, tolud, delta_cbmem; u32 pcie_config_base, pcie_config_size; u32 uma_sizek = 0; @@ -82,20 +83,8 @@ static void mch_domain_read_resources(struct device *dev) uma_sizek += gsm_sizek; printk(BIOS_DEBUG, "TSEG decoded, subtracting "); - reg8 = pci_read_config8(mch, D0F0_ESMRAMC); - reg8 >>= 1; - reg8 &= 3; - switch (reg8) { - case 0: - tseg_sizek = 1024; - break; /* TSEG = 1M */ - case 1: - tseg_sizek = 2048; - break; /* TSEG = 2M */ - case 2: - tseg_sizek = 8192; - break; /* TSEG = 8M */ - } + const u32 tseg_sizek = decode_tseg_size( + pci_read_config8(dev, D0F0_ESMRAMC)) >> 10; uma_sizek += tseg_sizek; tomk -= tseg_sizek; @@ -184,6 +173,36 @@ static const char *northbridge_acpi_name(const struct device *dev) return NULL; } +void northbridge_write_smram(u8 smram) +{ + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + + if (dev == NULL) + die("could not find pci 00:00.0!\n"); + + pci_write_config8(dev, D0F0_SMRAM, smram); +} + +/* + * Really doesn't belong here but will go away with parallel mp init, + * so let it be here for a while... + */ +int cpu_get_apic_id_map(int *apic_id_map) +{ + unsigned int i; + + /* Logical processors (threads) per core */ + const struct cpuid_result cpuid1 = cpuid(1); + /* Read number of cores. */ + const char cores = (cpuid1.ebx >> 16) & 0xf; + + /* TODO in parallel MP cpuid(1).ebx */ + for (i = 0; i < cores; i++) + apic_id_map[i] = i; + + return cores; +} + static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index 1f1c13f092..6484326e57 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -28,6 +28,7 @@ #include <cpu/x86/mtrr.h> #include <northbridge/intel/x4x/x4x.h> #include <program_loading.h> +#include <cpu/intel/smm/gen1/smi.h> /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ u32 decode_igd_memory_size(const u32 gms) @@ -52,6 +53,25 @@ u32 decode_igd_gtt_size(const u32 gsm) return ggc2gtt[gsm] << 10; } +/** Decodes used TSEG size to bytes. */ +u32 decode_tseg_size(const u32 esmramc) +{ + if (!(esmramc & 1)) + return 0; + + switch ((esmramc >> 1) & 3) { + case 0: + return 1 << 20; + case 1: + return 2 << 20; + case 2: + return 8 << 20; + case 3: + default: + die("Bad TSEG setting.\n"); + } +} + u8 decode_pciebar(u32 *const base, u32 *const len) { *base = 0; @@ -92,14 +112,25 @@ u8 decode_pciebar(u32 *const base, u32 *const len) return 1; } +u32 northbridge_get_tseg_size(void) +{ + const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); + return decode_tseg_size(esmramc); +} + +u32 northbridge_get_tseg_base(void) +{ + return pci_read_config32(PCI_DEV(0, 0, 0), D0F0_TSEG); +} + + /* Depending of UMA and TSEG configuration, TSEG might start at any * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ void *cbmem_top(void) { - uintptr_t top_of_ram = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_TSEG); - top_of_ram = ALIGN_DOWN(top_of_ram, 4*MiB); + uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); return (void *) top_of_ram; } @@ -122,14 +153,14 @@ void platform_enter_postcar(void) /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - /* Cache two separate 4 MiB regions below the top of ram, this - * satisfies MTRR alignment requirements. If you modify this to - * cover TSEG, make sure UMA region is not set with WRBACK as it - * causes hard-to-recover boot failures. + /* Cache 8 MiB region below the top of ram and 2 MiB above top of + * ram to cover both cbmem as the TSEG region. */ top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, + MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), + northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); run_postcar_phase(&pcf); diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 9837063641..a7efb172c5 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -373,6 +373,7 @@ void x4x_early_init(void); void x4x_late_init(int s3resume); u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); +u32 decode_tseg_size(const u32 esmramc); u8 decode_pciebar(u32 *const base, u32 *const len); void sdram_initialize(int boot_path, const u8 *spd_map); void do_raminit(struct sysinfo *, int fast_boot); diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index 1053659d68..c21a61a757 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -31,8 +31,6 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c ramstage-y += ../i82801gx/watchdog.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += early_smbus.c |