diff options
| -rw-r--r-- | src/soc/intel/apollolake/cse.c | 13 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/me.c | 21 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cse/cse.c | 22 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cse.h | 20 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/me.h | 5 | ||||
| -rw-r--r-- | src/soc/intel/skylake/me.c | 13 |
6 files changed, 63 insertions, 31 deletions
diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index 82226ecf43..260c6c6dc6 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -28,12 +28,6 @@ #include <device/pci_ops.h> #include <stdint.h> -#define PCI_ME_HFSTS1 0x40 -#define PCI_ME_HFSTS2 0x48 -#define PCI_ME_HFSTS3 0x60 -#define PCI_ME_HFSTS4 0x64 -#define PCI_ME_HFSTS5 0x68 -#define PCI_ME_HFSTS6 0x6c #define MKHI_GROUP_ID_MCA 0x0a #define READ_FILE 0x02 @@ -188,7 +182,9 @@ static void fpf_blown(void *unused) static uint32_t dump_status(int index, int reg_addr) { - uint32_t reg = pci_read_config32(PCH_DEV_CSE, reg_addr); + uint32_t reg; + + reg = me_read_config32(reg_addr); printk(BIOS_DEBUG, "CSE FWSTS%d: 0x%08x\n", index, reg); @@ -256,6 +252,9 @@ static void dump_cse_state(void) { uint32_t fwsts1; + if (!is_cse_enabled()) + return; + fwsts1 = dump_status(1, PCI_ME_HFSTS1); dump_status(2, PCI_ME_HFSTS2); dump_status(3, PCI_ME_HFSTS3); diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c index b8b4245d43..cd94be5c24 100644 --- a/src/soc/intel/cannonlake/me.c +++ b/src/soc/intel/cannonlake/me.c @@ -32,16 +32,6 @@ enum { ME_WSTATE_NORMAL = 0x05, }; -/* HFSTS register offsets in PCI config space */ -enum { - PCI_ME_HFSTS1 = 0x40, - PCI_ME_HFSTS2 = 0x48, - PCI_ME_HFSTS3 = 0x60, - PCI_ME_HFSTS4 = 0x64, - PCI_ME_HFSTS5 = 0x68, - PCI_ME_HFSTS6 = 0x6C, -}; - /* Host Firmware Status Register 1 */ union hfsts1 { uint32_t raw; @@ -155,11 +145,6 @@ union hfsts6 { } __packed fields; }; -static uint32_t me_read_config32(int offset) -{ - return pci_read_config32(PCH_DEV_CSE, offset); -} - /* * From reading the documentation, this should work for both WHL and CML * platforms. Also, calling this function from dump_me_status() does not @@ -201,6 +186,9 @@ static void print_me_version(void *unused) if (!CONFIG(CONSOLE_SERIAL)) return; + if (!is_cse_enabled()) + return; + hfsts1.raw = me_read_config32(PCI_ME_HFSTS1); /* @@ -244,6 +232,9 @@ void dump_me_status(void *unused) union hfsts5 hfsts5; union hfsts6 hfsts6; + if (!is_cse_enabled()) + return; + hfsts1.raw = me_read_config32(PCI_ME_HFSTS1); hfsts2.raw = me_read_config32(PCI_ME_HFSTS2); hfsts3.raw = me_read_config32(PCI_ME_HFSTS3); diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 9520242d2e..1671970a19 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -503,6 +503,28 @@ int heci_reset(void) return 0; } +bool is_cse_enabled(void) +{ + const struct device *cse_dev = pcidev_path_on_root(PCH_DEVFN_CSE); + + if (!cse_dev || !cse_dev->enabled) { + printk(BIOS_WARNING, "HECI: No CSE device\n"); + return false; + } + + if (pci_read_config16(PCH_DEV_CSE, PCI_VENDOR_ID) == 0xFFFF) { + printk(BIOS_WARNING, "HECI: CSE device is hidden\n"); + return false; + } + + return true; +} + +uint32_t me_read_config32(int offset) +{ + return pci_read_config32(PCH_DEV_CSE, offset); +} + #if ENV_RAMSTAGE static void update_sec_bar(struct device *dev) diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 424d483cfa..bce615c172 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -19,6 +19,16 @@ #include <stdint.h> +/* HFSTS register offsets in PCI config space */ +enum { + PCI_ME_HFSTS1 = 0x40, + PCI_ME_HFSTS2 = 0x48, + PCI_ME_HFSTS3 = 0x60, + PCI_ME_HFSTS4 = 0x64, + PCI_ME_HFSTS5 = 0x68, + PCI_ME_HFSTS6 = 0x6C, +}; + /* set up device for use in early boot enviroument with temp bar */ void heci_init(uintptr_t bar); /* @@ -52,6 +62,16 @@ int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t */ int heci_reset(void); +/* Reads config value from a specified offset in the CSE PCI Config space. */ +uint32_t me_read_config32(int offset); + +/* + * Check if the CSE device is enabled in device tree. Also check if the device + * is visible on the PCI bus by reading config space. + * Return true if device present and config space enabled, else return false. + */ +bool is_cse_enabled(void); + #define BIOS_HOST_ADDR 0x00 #define HECI_MKHI_ADDR 0x07 diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index 5a9acd51f3..fbe5033d7c 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -21,7 +21,6 @@ /* * Management Engine PCI registers */ -#define PCI_ME_HFSTS1 0x40 #define ME_HFS_CWS_RESET 0 #define ME_HFS_CWS_INIT 1 #define ME_HFS_CWS_REC 2 @@ -169,7 +168,6 @@ union me_hfs2 { } __packed fields; }; -#define PCI_ME_HFSTS3 0x60 #define ME_HFS3_FW_SKU_CONSUMER 0x2 #define ME_HFS3_FW_SKU_CORPORATE 0x3 @@ -186,9 +184,6 @@ union me_hfs3 { } __packed fields; }; -#define PCI_ME_HFSTS4 0x64 -#define PCI_ME_HFSTS5 0x68 -#define PCI_ME_HFSTS6 0x6c #define ME_HFS6_FPF_NOT_COMMITTED 0x0 #define ME_HFS6_FPF_ERROR 0x2 diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index f7aa584f37..9e17ef1e3d 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -26,10 +26,6 @@ #include <stdlib.h> #include <string.h> -static inline u32 me_read_config32(int offset) -{ - return pci_read_config32(PCH_DEV_CSE, offset); -} /* HFSTS1[3:0] Current Working State Values */ static const char *const me_cws_values[] = { @@ -242,6 +238,9 @@ static void print_me_version(void *unused) if (!CONFIG(CONSOLE_SERIAL)) return; + if (!is_cse_enabled()) + return; + hfs.data = me_read_config32(PCI_ME_HFSTS1); /* * This command can be run only if: @@ -288,6 +287,9 @@ void intel_me_status(void) union me_hfs3 hfs3; union me_hfs6 hfs6; + if (!is_cse_enabled()) + return; + hfs.data = me_read_config32(PCI_ME_HFSTS1); hfs2.data = me_read_config32(PCI_ME_HFSTS2); hfs3.data = me_read_config32(PCI_ME_HFSTS3); @@ -484,6 +486,9 @@ int send_global_reset(void) int status = -1; union me_hfs hfs; + if (!is_cse_enabled()) + goto ret; + /* Check ME operating mode */ hfs.data = me_read_config32(PCI_ME_HFSTS1); if (hfs.fields.operation_mode) |