diff options
| -rw-r--r-- | src/southbridge/intel/common/Kconfig | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/common/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/common/pmclib.c | 52 | ||||
| -rw-r--r-- | src/southbridge/intel/common/pmclib.h | 26 |
4 files changed, 84 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 6a96277844..0bda06e10a 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -6,6 +6,10 @@ config SOUTHBRIDGE_INTEL_COMMON_RESET bool select HAVE_CF9_RESET +config SOUTHBRIDGE_INTEL_COMMON_PMCLIB + def_bool n + depends on SOUTHBRIDGE_INTEL_COMMON + config SOUTHBRIDGE_INTEL_COMMON_GPIO def_bool n diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 3ad79248a0..ac339a2915 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -25,6 +25,8 @@ postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c +romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB) += pmclib.c + ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) romstage-y += pmbase.c diff --git a/src/southbridge/intel/common/pmclib.c b/src/southbridge/intel/common/pmclib.c new file mode 100644 index 0000000000..198562baee --- /dev/null +++ b/src/southbridge/intel/common/pmclib.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/acpi.h> +#include <console/console.h> + +#include "pmclib.h" +#include "pmbase.h" +#include "pmutil.h" + +int southbridge_detect_s3_resume(void) +{ + u32 pm1_cnt; + u16 pm1_sts; + int is_s3 = 0; + + /* Check PM1_STS[15] to see if we are waking from Sx */ + pm1_sts = read_pmbase16(PM1_STS); + if (pm1_sts & WAK_STS) { + /* Read PM1_CNT[12:10] to determine which Sx state */ + pm1_cnt = read_pmbase32(PM1_CNT); + if (((pm1_cnt >> 10) & 7) == SLP_TYP_S3) { + /* Clear SLP_TYPE. */ + write_pmbase32(PM1_CNT, pm1_cnt & ~(7 << 10)); + is_s3 = 1; + } + } + if (is_s3) { + if (!acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "SB: Resume from S3 detected, but disabled.\n"); + return 0; + } + + printk(BIOS_DEBUG, "SB: Resume from S3 detected.\n"); + } + + return is_s3; +} diff --git a/src/southbridge/intel/common/pmclib.h b/src/southbridge/intel/common/pmclib.h new file mode 100644 index 0000000000..7de5f97074 --- /dev/null +++ b/src/southbridge/intel/common/pmclib.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef INTEL_COMMON_PMCLIB_H +#define INTEL_COMMON_PMCLIB_H + +/* + * Returns 1 if platform was in ACPI S3 power state and CONFIG(ACPI_RESUME) + * is enabled else returns 0. + */ +int southbridge_detect_s3_resume(void); + +#endif |