diff options
| -rw-r--r-- | src/northbridge/intel/haswell/chip.h | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/gma.c | 5 |
2 files changed, 6 insertions, 1 deletions
diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index 098bc335f9..fdabc3fc9a 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -40,6 +40,8 @@ struct northbridge_intel_haswell_config { u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ + bool gpu_ddi_e_connected; + struct i915_gpu_controller_info gfx; }; diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index efc9fa3bd5..f4cec68c06 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -368,7 +368,10 @@ static void gma_setup_panel(struct device *dev) bit 4: DDI A supports 4 lanes and DDI E is not used bit 7: DDI buffer is idle */ - gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED); + reg32 = DDI_BUF_IS_IDLE | DDI_INIT_DISPLAY_DETECTED; + if (!conf->gpu_ddi_e_connected) + reg32 |= DDI_A_4_LANES; + gtt_write(DDI_BUF_CTL_A, reg32); /* Set FDI registers - is this required? */ gtt_write(_FDI_RXA_MISC, 0x00200090); |