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-rw-r--r--src/soc/intel/xeon_sp/Kconfig2
-rw-r--r--src/soc/intel/xeon_sp/memmap.c23
2 files changed, 16 insertions, 9 deletions
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index 6c10c35039..d84a80e12a 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -67,6 +67,8 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_SMI_HANDLER
select X86_SMM_LOADER_VERSION2
select REG_SCRIPT
+ select NO_FSP_TEMP_RAM_EXIT
+ select INTEL_CAR_NEM # For postcar only now
config MAINBOARD_USES_FSP2_0
bool
diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c
index cd817540b7..0af0ad2f6b 100644
--- a/src/soc/intel/xeon_sp/memmap.c
+++ b/src/soc/intel/xeon_sp/memmap.c
@@ -29,17 +29,22 @@ void smm_region(uintptr_t *start, size_t *size)
void fill_postcar_frame(struct postcar_frame *pcf)
{
- /*
- * We need to make sure ramstage will be run cached. At this
- * point exact location of ramstage in cbmem is not known.
- * Instruct postcar to cache 16 megs under cbmem top which is
- * a safe bet to cover ramstage.
- */
- uintptr_t top_of_ram = (uintptr_t)cbmem_top();
+ const uintptr_t top_of_ram = (uintptr_t)cbmem_top();
+ uintptr_t cbmem_base;
+ size_t cbmem_size;
+ /* Try account for the CBMEM region currently used and for future use */
+ cbmem_get_region((void **)&cbmem_base, &cbmem_size);
printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
- top_of_ram -= 16 * MiB;
- postcar_frame_add_mtrr(pcf, top_of_ram, 16 * MiB, MTRR_TYPE_WRBACK);
+ printk(BIOS_DEBUG, "cbmem base_ptr: 0x%lx, size: 0x%lx\n", cbmem_base, cbmem_size);
+ /* Assume 4MiB will be enough for future cbmem objects (FSP-S, ramstage, ...) */
+ cbmem_base -= 4 * MiB;
+ cbmem_base = ALIGN_DOWN(cbmem_base, 4 * MiB);
+
+ /* Align the top to make sure we don't use too many MTRR's */
+ cbmem_size = ALIGN_UP(top_of_ram - cbmem_base, 4 * MiB);
+
+ postcar_frame_add_mtrr(pcf, cbmem_base, cbmem_size, MTRR_TYPE_WRBACK);
/* Cache the TSEG region */
if (CONFIG(TSEG_STAGE_CACHE))
postcar_enable_tseg_cache(pcf);