diff options
| -rw-r--r-- | src/southbridge/intel/lynxpoint/azalia.c | 8 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/lpc.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pch.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pcie.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pmutil.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/sata.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/usb_xhci.c | 4 |
7 files changed, 11 insertions, 11 deletions
diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index 35dc63c5e8..0b1acdd409 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -48,7 +48,7 @@ static void azalia_pch_init(struct device *dev, u8 *base) u16 reg16; u32 reg32; - if (RCBA32(0x2030) & (1 << 31)) { + if (RCBA32(0x2030) & (1UL << 31)) { reg32 = pci_read_config32(dev, 0x120); reg32 &= 0xf8ffff01; reg32 |= (1 << 25); @@ -72,9 +72,9 @@ static void azalia_pch_init(struct device *dev, u8 *base) (1 << 25) | (1 << 26))) { reg32 = pci_read_config32(dev, 0x120); if (pch_is_lp()) - reg32 &= ~(1 << 31); + reg32 &= ~(1UL << 31); else - reg32 |= (1 << 31); + reg32 |= (1UL << 31); pci_write_config32(dev, 0x120, reg32); } @@ -101,7 +101,7 @@ static void azalia_pch_init(struct device *dev, u8 *base) if (!pch_is_lp()) { reg32 = pci_read_config32(dev, 0xd0); - reg32 &= ~(1 << 31); + reg32 &= ~(1UL << 31); pci_write_config32(dev, 0xd0, reg32); } diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index d295c888f8..6c4acd8c04 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -429,7 +429,7 @@ static void enable_clock_gating(device_t dev) reg32 = RCBA32(CG); reg32 |= (1 << 22); // HDA Dynamic - reg32 |= (1 << 31); // LPC Dynamic + reg32 |= (1UL << 31); // LPC Dynamic reg32 |= (1 << 16); // PCIe Dynamic reg32 |= (1 << 27); // HPET Dynamic reg32 |= (1 << 28); // GPIO Dynamic diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 8cae50a949..d76faf74dd 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -547,7 +547,7 @@ void pch_enable_lpc(void); #define RPFN 0x0404 /* 32bit */ /* Root Port configuratinon space hide */ -#define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) +#define RPFN_HIDE(port) (1UL << (((port) * 4) + 3)) /* Get the function number assigned to a Root Port */ #define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) /* Set the function number for a Root Port */ diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 3fd8d1e1c5..3d01cd6660 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -608,7 +608,7 @@ static void pch_pcie_early(struct device *dev) pci_update_config32(dev, 0x64, ~(1 << 11), (1 << 11)); pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10)); - pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); + pci_update_config32(dev, 0x318, ~(0xffffUL << 16), (0x1414UL << 16)); /* Set L1 exit latency in LCAP register. */ if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1)) diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index 90045d1be0..d895c56df1 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -45,7 +45,7 @@ static void print_status_bits(u32 status, const char *bit_names[]) return; for (i=31; i>=0; i--) { - if (status & (1 << i)) { + if (status & (1UL << i)) { if (bit_names[i]) printk(BIOS_DEBUG, "%s ", bit_names[i]); else diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 98cd0bc4b1..31081d7810 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -297,7 +297,7 @@ static void sata_init(struct device *dev) reg32 = pci_read_config32(dev, 0x300); reg32 |= (1 << 17) | (1 << 16); - reg32 |= (1 << 31) | (1 << 30) | (1 << 29); + reg32 |= (1UL << 31) | (1 << 30) | (1 << 29); pci_write_config32(dev, 0x300, reg32); } diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 0acf35ff7c..28e6521598 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -342,13 +342,13 @@ static void usb_xhci_init(device_t dev) /* D20:F0:44h[31] = 1 (Access Control Bit) */ reg32 = pci_read_config32(dev, 0x44); - reg32 |= (1 << 31); + reg32 |= (1UL << 31); pci_write_config32(dev, 0x44, reg32); /* D20:F0:40h[31,23] = 10b (OC Configuration Done) */ reg32 = pci_read_config32(dev, 0x40); reg32 &= ~(1 << 23); /* unsupported request */ - reg32 |= (1 << 31); + reg32 |= (1UL << 31); pci_write_config32(dev, 0x40, reg32); if (acpi_is_wakeup_s3()) { |