diff options
| -rw-r--r-- | src/cpu/Kconfig | 3 | ||||
| -rw-r--r-- | src/cpu/amd/car/cache_as_ram.inc | 15 | ||||
| -rw-r--r-- | src/cpu/amd/geode_gx2/Kconfig | 4 | ||||
| -rw-r--r-- | src/cpu/amd/geode_lx/Kconfig | 4 | ||||
| -rw-r--r-- | src/cpu/amd/model_10xxx/Kconfig | 4 | ||||
| -rw-r--r-- | src/cpu/amd/model_10xxx/init_cpus.c | 5 | ||||
| -rw-r--r-- | src/cpu/amd/socket_754/Kconfig | 4 | ||||
| -rw-r--r-- | src/cpu/amd/socket_940/Kconfig | 4 | ||||
| -rw-r--r-- | src/cpu/amd/socket_S1G1/Kconfig | 4 |
9 files changed, 43 insertions, 4 deletions
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index ae2e88c7d4..bfe00fe4e8 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -19,6 +19,9 @@ config DCACHE_RAM_SIZE config DCACHE_BSP_STACK_SIZE hex +config DCACHE_BSP_STACK_SLUSH + hex + config DCACHE_AP_STACK_SIZE hex diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 51ebba60f7..ac6ea33b98 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -26,6 +26,7 @@ #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase (0xd0000 - CacheSize) #define CacheSizeBSPStack CONFIG_DCACHE_BSP_STACK_SIZE +#define CacheSizeBSPSlush CONFIG_DCACHE_BSP_STACK_SLUSH /* For CAR with Fam10h. */ #define CacheSizeAPStack CONFIG_DCACHE_AP_STACK_SIZE @@ -377,9 +378,17 @@ CAR_FAM10_ap: /* * Need to set stack pointer for AP. * It will be from: - * CacheBase + CacheSize / 2 + * CacheBase + (CacheSize - (CacheSizeBSPStack + CacheSizeBSPSlush)) * - (NodeID << CoreIDbits + CoreID) * CacheSizeAPStack - * So need to get the NodeID and CoreID at first. + * The spacing between the BSP stack and the top of the AP + * stacks is purposefully set larger (an extra CacheSizeBSPSlush + * worth of unused space) than necessary to aid debugging when + * additional stack variables are added by future developers. + * The extra space will allow BSP overruns to be caught by + * the warning logic and easily fixed instead of crashing the + * system with no obvious clues of what went wrong. + * + * So, need to get the NodeID and CoreID at first. * If NB_CFG bit 54 is set just use initial APIC ID, otherwise need * to reverse it. */ @@ -411,7 +420,7 @@ roll_cfg: /* Calculate stack pointer. */ movl $CacheSizeAPStack, %eax mull %ebx - movl $(CacheBase + CacheSize / 2), %esp + movl $(CacheBase + (CacheSize - (CacheSizeBSPStack + CacheSizeBSPSlush))), %esp subl %eax, %esp /* Retrive init detected. */ diff --git a/src/cpu/amd/geode_gx2/Kconfig b/src/cpu/amd/geode_gx2/Kconfig index b867e3701b..1b56d5d4b1 100644 --- a/src/cpu/amd/geode_gx2/Kconfig +++ b/src/cpu/amd/geode_gx2/Kconfig @@ -41,6 +41,10 @@ config DCACHE_BSP_STACK_SIZE hex default 0x1000 +config DCACHE_BSP_STACK_SLUSH + hex + default 0x1000 + config DCACHE_AP_STACK_SIZE hex default 0x400 diff --git a/src/cpu/amd/geode_lx/Kconfig b/src/cpu/amd/geode_lx/Kconfig index d799d6b394..d707bea980 100644 --- a/src/cpu/amd/geode_lx/Kconfig +++ b/src/cpu/amd/geode_lx/Kconfig @@ -23,6 +23,10 @@ config DCACHE_BSP_STACK_SIZE hex default 0x2000 +config DCACHE_BSP_STACK_SLUSH + hex + default 0x1000 + config DCACHE_AP_STACK_SIZE hex default 0x400 diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index 4b5cdedaa1..ebd282a5ca 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -34,6 +34,10 @@ config DCACHE_BSP_STACK_SIZE hex default 0x2000 +config DCACHE_BSP_STACK_SLUSH + hex + default 0x1000 + config DCACHE_AP_STACK_SIZE hex default 0x400 diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 7e79307c89..4c72848986 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -250,8 +250,11 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) u32 apicid; struct node_core_id id; + /* Please refer to the calculations and explaination in cache_as_ram.inc before modifying these values */ uint32_t max_ap_stack_region_size = CONFIG_MAX_CPUS * CONFIG_DCACHE_AP_STACK_SIZE; - uint32_t bsp_stack_region_lower_boundary = CONFIG_DCACHE_RAM_BASE + (CONFIG_DCACHE_RAM_SIZE / 2); + uint32_t max_bsp_stack_region_size = CONFIG_DCACHE_BSP_STACK_SIZE + CONFIG_DCACHE_BSP_STACK_SLUSH; + uint32_t bsp_stack_region_upper_boundary = CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE; + uint32_t bsp_stack_region_lower_boundary = bsp_stack_region_upper_boundary - max_bsp_stack_region_size; void * lower_stack_region_boundary = (void*)(bsp_stack_region_lower_boundary - max_ap_stack_region_size); if (((void*)(sysinfo + 1)) > lower_stack_region_boundary) printk(BIOS_WARNING, diff --git a/src/cpu/amd/socket_754/Kconfig b/src/cpu/amd/socket_754/Kconfig index 395fc788c4..aeda4210f4 100644 --- a/src/cpu/amd/socket_754/Kconfig +++ b/src/cpu/amd/socket_754/Kconfig @@ -24,6 +24,10 @@ config DCACHE_BSP_STACK_SIZE hex default 0x2000 +config DCACHE_BSP_STACK_SLUSH + hex + default 0x1000 + config DCACHE_AP_STACK_SIZE hex default 0x400 diff --git a/src/cpu/amd/socket_940/Kconfig b/src/cpu/amd/socket_940/Kconfig index a481ded55a..a8eef61b0f 100644 --- a/src/cpu/amd/socket_940/Kconfig +++ b/src/cpu/amd/socket_940/Kconfig @@ -25,6 +25,10 @@ config DCACHE_BSP_STACK_SIZE hex default 0x2000 +config DCACHE_BSP_STACK_SLUSH + hex + default 0x1000 + config DCACHE_AP_STACK_SIZE hex default 0x400 diff --git a/src/cpu/amd/socket_S1G1/Kconfig b/src/cpu/amd/socket_S1G1/Kconfig index 2c79e1fca5..01d84a1d3a 100644 --- a/src/cpu/amd/socket_S1G1/Kconfig +++ b/src/cpu/amd/socket_S1G1/Kconfig @@ -35,6 +35,10 @@ config DCACHE_BSP_STACK_SIZE hex default 0x2000 +config DCACHE_BSP_STACK_SLUSH + hex + default 0x1000 + config DCACHE_AP_STACK_SIZE hex default 0x400 |