diff options
| -rw-r--r-- | src/cpu/intel/model_2065x/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/cpu/intel/model_2065x/model_2065x.h | 11 | ||||
| -rw-r--r-- | src/cpu/intel/model_2065x/stage_cache.c | 30 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/model_206ax.h | 12 | ||||
| -rw-r--r-- | src/cpu/intel/model_206ax/stage_cache.c | 28 | ||||
| -rw-r--r-- | src/northbridge/intel/nehalem/nehalem.h | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/nehalem/northbridge.c | 5 | ||||
| -rw-r--r-- | src/northbridge/intel/nehalem/ram_calc.c | 15 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 22 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/ram_calc.c | 28 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/sandybridge.h | 4 |
12 files changed, 40 insertions, 126 deletions
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index 9a11b06e4d..1f6d1a22b9 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -19,10 +19,6 @@ ramstage-y += acpi.c smm-y += finalize.c -romstage-y += stage_cache.c -ramstage-y += stage_cache.c -postcar-y += stage_cache.c - cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-25-*) cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index eab2dd5c50..2f3584a67e 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -80,16 +80,9 @@ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); #endif -/* - * Region of SMM space is reserved for multipurpose use. It falls below - * the IED region and above the SMM handler. - */ -#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE -#define RESERVED_SMM_OFFSET (CONFIG_SMM_TSEG_SIZE - RESERVED_SMM_SIZE) - /* Sanity check config options. */ -#if (CONFIG_SMM_TSEG_SIZE <= RESERVED_SMM_SIZE) -# error "CONFIG_SMM_TSEG_SIZE <= RESERVED_SMM_SIZE" +#if (CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE) +# error "CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE" #endif #if (CONFIG_SMM_TSEG_SIZE < 0x800000) # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" diff --git a/src/cpu/intel/model_2065x/stage_cache.c b/src/cpu/intel/model_2065x/stage_cache.c deleted file mode 100644 index ab8ac979c1..0000000000 --- a/src/cpu/intel/model_2065x/stage_cache.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <stage_cache.h> -#include <cpu/intel/smm/gen1/smi.h> -#include "model_2065x.h" - -void stage_cache_external_region(void **base, size_t *size) -{ - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. - */ - *size = RESERVED_SMM_SIZE; - *base = (void *)((uintptr_t)northbridge_get_tseg_base() - + RESERVED_SMM_OFFSET); -} diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index f5de8c38fa..e723d74d78 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -24,10 +24,6 @@ smm-y += tsc_freq.c smm-y += finalize.c -romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c -ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c - cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*) cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3a-*) diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index c0d2434fe6..2dc929345d 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -81,17 +81,9 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10 -/* - * Region of SMM space is reserved for multipurpose use. It falls below - * the IED region and above the SMM handler. - */ -#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE -#define RESERVED_SMM_OFFSET \ - (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE) - /* Sanity check config options. */ -#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)) -# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)" +#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)) +# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)" #endif #if (CONFIG_SMM_TSEG_SIZE < 0x800000) # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" diff --git a/src/cpu/intel/model_206ax/stage_cache.c b/src/cpu/intel/model_206ax/stage_cache.c deleted file mode 100644 index 26dc5e03f9..0000000000 --- a/src/cpu/intel/model_206ax/stage_cache.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <stage_cache.h> -#include "model_206ax.h" - -void stage_cache_external_region(void **base, size_t *size) -{ - /* - * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. - */ - *size = RESERVED_SMM_SIZE; - *base = (void *)((uintptr_t)cbmem_top() + RESERVED_SMM_OFFSET); -} diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index b220c2d7a9..93024f69d8 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -122,9 +122,6 @@ typedef struct { #define IVB_STEP_K0 (BASE_REV_IVB + 5) #define IVB_STEP_D0 (BASE_REV_IVB + 6) -/* Intel Enhanced Debug region must be 4MB */ -#define IED_SIZE 0x400000 - /* Northbridge BARs */ #ifndef __ACPI__ #define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 485cb27f45..a058d3fa26 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -171,11 +171,6 @@ static void mc_read_resources(struct device *dev) add_fixed_resources(dev, 10); } -u32 northbridge_get_tseg_size(void) -{ - return CONFIG_SMM_TSEG_SIZE; -} - static void mc_set_resources(struct device *dev) { /* And call the normal set_resources */ diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c index ba3761065b..ec036c9d7c 100644 --- a/src/northbridge/intel/nehalem/ram_calc.c +++ b/src/northbridge/intel/nehalem/ram_calc.c @@ -23,6 +23,7 @@ #include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> +#include <stage_cache.h> #include <cpu/intel/smm/gen1/smi.h> #include "nehalem.h" @@ -38,11 +39,25 @@ u32 northbridge_get_tseg_base(void) return (u32)smm_region_start(); } +u32 northbridge_get_tseg_size(void) +{ + return CONFIG_SMM_TSEG_SIZE; +} + void *cbmem_top(void) { return (void *) smm_region_start(); } +void stage_cache_external_region(void **base, size_t *size) +{ + /* The stage cache lives at the end of TSEG region. + * The top of RAM is defined to be the TSEG base address. */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); +} + /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 5aa06c8e4f..233384cd15 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -444,28 +444,6 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static u32 northbridge_get_base_reg(struct device *dev, int reg) -{ - u32 value; - - value = pci_read_config32(dev, reg); - /* Base registers are at 1MiB granularity. */ - value &= ~((1 << 20) - 1); - return value; -} - -u32 northbridge_get_tseg_base(void) -{ - struct device *dev = pcidev_on_root(0, 0); - - return northbridge_get_base_reg(dev, TSEG); -} - -u32 northbridge_get_tseg_size(void) -{ - return CONFIG_SMM_TSEG_SIZE; -} - void northbridge_write_smram(u8 smram) { pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram); diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c index 343ae62711..7d5c173829 100644 --- a/src/northbridge/intel/sandybridge/ram_calc.c +++ b/src/northbridge/intel/sandybridge/ram_calc.c @@ -20,17 +20,12 @@ #include <cbmem.h> #include <console/console.h> #include <cpu/intel/romstage.h> +#include <cpu/intel/smm/gen1/smi.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> +#include <stage_cache.h> #include "sandybridge.h" -#if (CONFIG_SMM_TSEG_SIZE < 0x800000) -# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" -#endif -#if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0) -# error "CONFIG_SMM_TSEG_SIZE is not a power of 2" -#endif - static uintptr_t smm_region_start(void) { /* Base of TSEG is top of usable DRAM */ @@ -43,6 +38,25 @@ void *cbmem_top(void) return (void *) smm_region_start(); } +u32 northbridge_get_tseg_base(void) +{ + return ALIGN_DOWN(smm_region_start(), 1*MiB); +} + +u32 northbridge_get_tseg_size(void) +{ + return CONFIG_SMM_TSEG_SIZE; +} + +void stage_cache_external_region(void **base, size_t *size) +{ + /* The stage cache lives at the end of TSEG region. + * The top of RAM is defined to be the TSEG base address. */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + northbridge_get_tseg_size() + - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE); +} + /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 88b7b56864..b488f2c249 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -34,10 +34,6 @@ #define IVB_STEP_K0 (BASE_REV_IVB + 5) #define IVB_STEP_D0 (BASE_REV_IVB + 6) -/* Intel Enhanced Debug region must be 4MB */ - -#define IED_SIZE CONFIG_IED_REGION_SIZE - /* Northbridge BARs */ #ifndef __ACPI__ #define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ |