diff options
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/registers/mchbar.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 2c16818700..b45c44267c 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1711,7 +1711,7 @@ static void train_write_flyby(ramctr_timing *ctrl) .rank = slotrank, }, }, - /* DRAM command RD */ + /* DRAM command RDA */ [2] = { .sp_cmd_ctrl = { .command = IOSAV_RD, diff --git a/src/northbridge/intel/sandybridge/registers/mchbar.h b/src/northbridge/intel/sandybridge/registers/mchbar.h index d3df3c0d96..bdf85dc3b3 100644 --- a/src/northbridge/intel/sandybridge/registers/mchbar.h +++ b/src/northbridge/intel/sandybridge/registers/mchbar.h @@ -112,7 +112,7 @@ * end architecture RTL; * * [16] Chip Select mode control. - * [17] Auto Precharge. Only valid when using 10 row bits! + * [17] Auto Precharge. Used to send RDA commands. * * IOSAV_n_SUBSEQ_CTRL_ch(channel, index) * The parameters of the subseq: number of repetitions of the command, |