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-rw-r--r--src/mainboard/google/chell/devicetree.cb1
-rw-r--r--src/mainboard/google/eve/devicetree.cb1
-rw-r--r--src/mainboard/google/fizz/devicetree.cb1
-rw-r--r--src/mainboard/google/glados/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/baseboard/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/nami/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/nautilus/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/soraka/devicetree.cb1
-rw-r--r--src/mainboard/intel/saddlebrook/devicetree.cb1
-rw-r--r--src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb1
-rw-r--r--src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb1
-rw-r--r--src/soc/intel/skylake/Kconfig1
-rw-r--r--src/soc/intel/skylake/chip.c10
-rw-r--r--src/soc/intel/skylake/chip.h1
-rw-r--r--src/soc/intel/skylake/chip_fsp20.c8
15 files changed, 16 insertions, 15 deletions
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index f8c3054012..2f077539a9 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -36,7 +36,6 @@ chip soc/intel/skylake
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
- register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 2e62f41fbb..f24d5c9cea 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -32,7 +32,6 @@ chip soc/intel/skylake
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
- register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index a9646ec6cb..9d120ea9cf 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -67,7 +67,6 @@ chip soc/intel/skylake
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
- register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 0dff3d95dd..94d9e53eb2 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -36,7 +36,6 @@ chip soc/intel/skylake
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
- register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 074e8a2a4c..032c42634a 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -38,7 +38,6 @@ chip soc/intel/skylake
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
- register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "1"
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index 0b3387e2de..a04dd95e8d 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -34,7 +34,6 @@ chip soc/intel/skylake
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
- register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index 6946b38f14..8a946823fa 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -38,7 +38,6 @@ chip soc/intel/skylake
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
- register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "1"
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index 65955eb7d9..2688d58148 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -38,7 +38,6 @@ chip soc/intel/skylake
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
- register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "1"
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index 7903ddcd39..6da73dc412 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -170,7 +170,6 @@ chip soc/intel/skylake
# USB related
register "SsicPortEnable" = "1"
- register "XdciEnable" = "0"
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # OTG
register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Touch Pad
diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
index 50e484b0df..b3c5ffb51d 100644
--- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
@@ -41,7 +41,6 @@ chip soc/intel/skylake
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "EnableTraceHub" = "0"
- register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
index a52e4b7e3f..bf57398e9a 100644
--- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
@@ -41,7 +41,6 @@ chip soc/intel/skylake
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "EnableTraceHub" = "0"
- register "XdciEnable" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 832d7e242a..2322a5f2c7 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -85,6 +85,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_TIMER
select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_BLOCK_VMX
+ select SOC_INTEL_COMMON_BLOCK_XDCI
select SOC_INTEL_COMMON_BLOCK_XHCI
select SOC_INTEL_COMMON_GFX_OPREGION
select SOC_INTEL_COMMON_NHLT
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index f60c08d97c..0c1dfa65e5 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -20,6 +20,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <fsp/util.h>
+#include <intelblocks/xdci.h>
#include <soc/acpi.h>
#include <soc/interrupt.h>
#include <soc/irq.h>
@@ -78,7 +79,7 @@ struct chip_operations soc_intel_skylake_ops = {
/* UPD parameters to be initialized before SiliconInit */
void soc_silicon_init_params(SILICON_INIT_UPD *params)
{
- const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+ struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
const struct soc_intel_skylake_config *config = dev->chip_info;
int i;
@@ -140,7 +141,6 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->EnableAzalia = config->EnableAzalia;
params->IoBufferOwnership = config->IoBufferOwnership;
params->DspEnable = config->DspEnable;
- params->XdciEnable = config->XdciEnable;
params->Device4Enable = config->Device4Enable;
params->EnableSata = config->EnableSata;
params->SataMode = config->SataMode;
@@ -196,6 +196,12 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
dev = dev_find_slot(0, PCH_DEVFN_SPI);
params->ShowSpiController = dev->enabled;
+ /* Enable xDCI controller if enabled in devicetree and allowed */
+ dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
+ if (!xdci_can_enable())
+ dev->enabled = 0;
+ params->XdciEnable = dev->enabled;
+
params->SendVrMbxCmd = config->SendVrMbxCmd;
/* Acoustic Noise Mitigation */
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index b77f6dc771..dc7986948f 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -237,7 +237,6 @@ struct soc_intel_skylake_config {
/* USB related */
struct usb2_port_config usb2_ports[16];
struct usb3_port_config usb3_ports[10];
- u8 XdciEnable;
u8 SsicPortEnable;
/* SMBus */
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 3bc66b2501..b4fed26d1d 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -26,6 +26,7 @@
#include <device/pci.h>
#include <fsp/api.h>
#include <fsp/util.h>
+#include <intelblocks/xdci.h>
#include <romstage_handoff.h>
#include <soc/acpi.h>
#include <soc/intel/common/vbt.h>
@@ -221,7 +222,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchHdaEnable = config->EnableAzalia;
params->PchHdaIoBufferOwnership = config->IoBufferOwnership;
params->PchHdaDspEnable = config->DspEnable;
- params->XdciEnable = config->XdciEnable;
params->Device4Enable = config->Device4Enable;
params->SataEnable = config->EnableSata;
params->SataMode = config->SataMode;
@@ -284,6 +284,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
dev = dev_find_slot(0, PCH_DEVFN_SPI);
params->ShowSpiController = dev->enabled;
+ /* Enable xDCI controller if enabled in devicetree and allowed */
+ dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
+ if (!xdci_can_enable())
+ dev->enabled = 0;
+ params->XdciEnable = dev->enabled;
+
/*
* Send VR specific mailbox commands:
* 000b - no VR specific command sent
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 06:59:23 +0000