diff options
| -rw-r--r-- | src/Kconfig | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/common/Kconfig.common | 17 | ||||
| -rw-r--r-- | src/northbridge/intel/common/fixed_bars.h | 24 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/Kconfig | 9 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/acpi/gm45.asl | 7 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/early_init.c | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/gm45.h | 12 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/memmap.h | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/pcie.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ix/dmi_setup.c | 3 |
10 files changed, 61 insertions, 26 deletions
diff --git a/src/Kconfig b/src/Kconfig index 33065cbddb..1e3b0d5c8b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -523,6 +523,7 @@ comment "CPU" source "src/cpu/Kconfig" comment "Northbridge" source "src/northbridge/*/*/Kconfig" +source "src/northbridge/*/*/Kconfig.common" comment "Southbridge" source "src/southbridge/*/*/Kconfig" comment "Super I/O" diff --git a/src/northbridge/intel/common/Kconfig.common b/src/northbridge/intel/common/Kconfig.common new file mode 100644 index 0000000000..4f231be314 --- /dev/null +++ b/src/northbridge/intel/common/Kconfig.common @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config NORTHBRIDGE_INTEL_COMMON + bool + +if NORTHBRIDGE_INTEL_COMMON + +config FIXED_DMIBAR_MMIO_BASE + hex + +config FIXED_EPBAR_MMIO_BASE + hex + +config FIXED_MCHBAR_MMIO_BASE + hex + +endif # NORTHBRIDGE_INTEL_COMMON diff --git a/src/northbridge/intel/common/fixed_bars.h b/src/northbridge/intel/common/fixed_bars.h new file mode 100644 index 0000000000..d1b005bfae --- /dev/null +++ b/src/northbridge/intel/common/fixed_bars.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef NORTHBRIDGE_INTEL_COMMON_FIXED_BARS_H +#define NORTHBRIDGE_INTEL_COMMON_FIXED_BARS_H + +_Static_assert(CONFIG_FIXED_MCHBAR_MMIO_BASE != 0, "MCHBAR base address is zero"); +_Static_assert(CONFIG_FIXED_DMIBAR_MMIO_BASE != 0, "DMIBAR base address is zero"); +_Static_assert(CONFIG_FIXED_EPBAR_MMIO_BASE != 0, "EPBAR base address is zero"); + +#include <stdint.h> + +#define MCHBAR8(x) (*((volatile u8 *)(CONFIG_FIXED_MCHBAR_MMIO_BASE + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(CONFIG_FIXED_MCHBAR_MMIO_BASE + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(CONFIG_FIXED_MCHBAR_MMIO_BASE + (x)))) + +#define DMIBAR8(x) (*((volatile u8 *)(CONFIG_FIXED_DMIBAR_MMIO_BASE + (x)))) +#define DMIBAR16(x) (*((volatile u16 *)(CONFIG_FIXED_DMIBAR_MMIO_BASE + (x)))) +#define DMIBAR32(x) (*((volatile u32 *)(CONFIG_FIXED_DMIBAR_MMIO_BASE + (x)))) + +#define EPBAR8(x) (*((volatile u8 *)(CONFIG_FIXED_EPBAR_MMIO_BASE + (x)))) +#define EPBAR16(x) (*((volatile u16 *)(CONFIG_FIXED_EPBAR_MMIO_BASE + (x)))) +#define EPBAR32(x) (*((volatile u32 *)(CONFIG_FIXED_EPBAR_MMIO_BASE + (x)))) + +#endif /* ! NORTHBRIDGE_INTEL_COMMON_FIXED_BARS_H */ diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 58942f07f3..06883e4da1 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -43,4 +43,13 @@ config INTEL_GMA_BCLV_OFFSET config INTEL_GMA_BCLM_OFFSET default 0x61256 +config FIXED_MCHBAR_MMIO_BASE + default 0xfed14000 + +config FIXED_DMIBAR_MMIO_BASE + default 0xfed18000 + +config FIXED_EPBAR_MMIO_BASE + default 0xfed19000 + endif diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index fc73f24e4f..43d73e922d 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include "hostbridge.asl" -#include "../memmap.h" #include <southbridge/intel/i82801ix/i82801ix.h> /* PCI Device Resource Consumption */ @@ -14,9 +13,9 @@ Device (PDRC) // now. Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) - Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) + Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index 86f71d6ff8..6e3ea2c7a3 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -10,13 +10,13 @@ void gm45_early_init(void) const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0); /* Setup MCHBAR. */ - pci_write_config32(d0f0, D0F0_MCHBAR_LO, DEFAULT_MCHBAR | 1); + pci_write_config32(d0f0, D0F0_MCHBAR_LO, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); /* Setup DMIBAR. */ - pci_write_config32(d0f0, D0F0_DMIBAR_LO, DEFAULT_DMIBAR | 1); + pci_write_config32(d0f0, D0F0_DMIBAR_LO, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1); /* Setup EPBAR. */ - pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1); + pci_write_config32(d0f0, D0F0_EPBAR_LO, CONFIG_FIXED_EPBAR_MMIO_BASE | 1); pci_write_config32(d0f0, D0F0_PMBASE, DEFAULT_PMBASE | 1); diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index ae8b8390ca..b6e7c2f2b1 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -218,9 +218,7 @@ enum { * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#include <northbridge/intel/common/fixed_bars.h> #define HPLLVCO_MCHBAR 0x0c0f @@ -342,10 +340,6 @@ enum { * DMIBAR */ -#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) -#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) -#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) - #define DMIVCECH 0x000 /* 32bit */ #define DMIPVCCAP1 0x004 /* 32bit */ @@ -374,10 +368,6 @@ enum { * EPBAR */ -#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) -#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) -#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) - #define EPPVCCAP1 0x004 /* 32bit */ #define EPPVCCTL 0x00c /* 32bit */ diff --git a/src/northbridge/intel/gm45/memmap.h b/src/northbridge/intel/gm45/memmap.h index c0706d0442..e582aa0110 100644 --- a/src/northbridge/intel/gm45/memmap.h +++ b/src/northbridge/intel/gm45/memmap.h @@ -3,10 +3,6 @@ #ifndef __NORTHBRIDGE_INTEL_GM45_MEMMAP_H__ #define __NORTHBRIDGE_INTEL_GM45_MEMMAP_H__ -#define DEFAULT_MCHBAR 0xfed14000 -#define DEFAULT_DMIBAR 0xfed18000 -#define DEFAULT_EPBAR 0xfed19000 - #define IOMMU_BASE1 0xfed90000 #define IOMMU_BASE2 0xfed91000 #define IOMMU_BASE3 0xfed92000 diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index f2c0090ed5..4ccd2d61ff 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -251,7 +251,7 @@ static void setup_rcrb(const int peg_enabled) /* Link1: component ID 1, link valid. */ EPBAR32(EPLE1D) = (EPBAR32(EPLE1D) & 0xff000000) | (1 << 16) | (1 << 0); - EPBAR32(EPLE1A) = DEFAULT_DMIBAR; + EPBAR32(EPLE1A) = CONFIG_FIXED_DMIBAR_MMIO_BASE; if (peg_enabled) /* Link2: link_valid. */ @@ -269,7 +269,7 @@ static void setup_rcrb(const int peg_enabled) /* Link2: component ID 1 (MCH), link valid */ DMIBAR32(DMILE2D) = (DMIBAR32(DMILE2D) & 0xff000000) | (1 << 16) | (1 << 0); - DMIBAR32(DMILE2A) = DEFAULT_MCHBAR; + DMIBAR32(DMILE2A) = CONFIG_FIXED_MCHBAR_MMIO_BASE; } void gm45_late_init(const stepping_t stepping) diff --git a/src/southbridge/intel/i82801ix/dmi_setup.c b/src/southbridge/intel/i82801ix/dmi_setup.c index cbb52c4a6c..f8b418d9df 100644 --- a/src/southbridge/intel/i82801ix/dmi_setup.c +++ b/src/southbridge/intel/i82801ix/dmi_setup.c @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <console/console.h> -#include <northbridge/intel/gm45/gm45.h> #include "i82801ix.h" /* VC1 Port Arbitration Table */ @@ -67,7 +66,7 @@ void i82801ix_dmi_setup(void) RCBA8(RCBA_ULD + 3) = 1; RCBA8(RCBA_ULD + 2) = 1; /* Set target rcrb base address, i.e. DMIBAR. */ - RCBA32(RCBA_ULBA) = (uintptr_t)DEFAULT_DMIBAR; + RCBA32(RCBA_ULBA) = (uintptr_t)CONFIG_FIXED_DMIBAR_MMIO_BASE; /* Enable ASPM. */ if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0))) { |