diff options
| -rw-r--r-- | src/cpu/amd/model_lx/msrinit.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/amd/model_lx/msrinit.c b/src/cpu/amd/model_lx/msrinit.c index 9c6e98e14c..11182501c1 100644 --- a/src/cpu/amd/model_lx/msrinit.c +++ b/src/cpu/amd/model_lx/msrinit.c @@ -22,10 +22,10 @@ static const msrinit_t msr_table[] = { - {CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB. + {CPU_RCONF_DEFAULT, {.hi = 0x24fffc00,.lo = 0x0000A000}}, /* Setup access to cache under 1MB. * Rom Properties: Write Serialize, WriteProtect. * RomBase: 0xFFFC0 - * SysTop to RomBase Properties: Write Serialize, Cache Disable. + * SysTop to RomBase Properties: Write Back. * SysTop: 0x000A0 * System Memory Properties: (Write Back) */ {CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */ |