diff options
| -rw-r--r-- | src/cpu/x86/mtrr/debug.c | 3 | ||||
| -rw-r--r-- | src/include/cpu/x86/mtrr.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/cpu.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/sgx/sgx.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/cpu.c | 2 |
5 files changed, 6 insertions, 4 deletions
diff --git a/src/cpu/x86/mtrr/debug.c b/src/cpu/x86/mtrr/debug.c index c33016026b..4ecae068b7 100644 --- a/src/cpu/x86/mtrr/debug.c +++ b/src/cpu/x86/mtrr/debug.c @@ -92,8 +92,9 @@ static void display_mtrrcap(void) msr = rdmsr(MTRR_CAP_MSR); printk(BIOS_DEBUG, - "0x%08x%08x: IA32_MTRRCAP: %s%s%s%u variable MTRRs\n", + "0x%08x%08x: IA32_MTRRCAP: %s%s%s%s%u variable MTRRs\n", msr.hi, msr.lo, + (msr.lo & MTRR_CAP_PRMRR) ? "PRMRR, " : "", (msr.lo & MTRR_CAP_SMRR) ? "SMRR, " : "", (msr.lo & MTRR_CAP_WC) ? "WC, " : "", (msr.lo & MTRR_CAP_FIX) ? "FIX, " : "", diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 9227710596..42964b02ea 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -16,6 +16,7 @@ #define MTRR_CAP_MSR 0x0fe +#define MTRR_CAP_PRMRR (1 << 12) #define MTRR_CAP_SMRR (1 << 11) #define MTRR_CAP_WC (1 << 10) #define MTRR_CAP_FIX (1 << 8) diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 26d8c2ea97..89d3493889 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -312,6 +312,6 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) if (msr2.lo && (current_patch_id == new_patch_id - 1)) return 0; - return (msr1.lo & PRMRR_SUPPORTED) && + return (msr1.lo & MTRR_CAP_PRMRR) && (current_patch_id == new_patch_id - 1); } diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index 5f14909361..56648c81ea 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -28,7 +28,7 @@ static int is_sgx_supported(void) cpuid_regs = cpuid_ext(0x7, 0x0); /* EBX[2] is feature capability */ msr = rdmsr(MTRR_CAP_MSR); /* Bit 12 is PRMRR enablement */ - return ((cpuid_regs.ebx & SGX_SUPPORTED) && (msr.lo & PRMRR_SUPPORTED)); + return ((cpuid_regs.ebx & SGX_SUPPORTED) && (msr.lo & MTRR_CAP_PRMRR)); } void prmrr_core_configure(void) diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 49d817ffef..a545435599 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -355,6 +355,6 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) if (msr2.lo && (current_patch_id == new_patch_id - 1)) return 0; else - return (msr1.lo & PRMRR_SUPPORTED) && + return (msr1.lo & MTRR_CAP_PRMRR) && (current_patch_id == new_patch_id - 1); } |