diff options
| -rw-r--r-- | src/mainboard/google/slippy/romstage.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index be1caa9425..e44e48527d 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -18,7 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <delay.h> #include <stdint.h> +#include <stdlib.h> #include <console/console.h> #include "cpu/intel/haswell/haswell.h" #include "northbridge/intel/haswell/haswell.h" @@ -71,6 +73,39 @@ const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; +/* + * Power Sequencing for SanDisk i100/i110 SSD + * + * Must be sequenced in this order with specified timing. + * + * 1. VCC_IO : 30us - 100ms + * 2. VCC_FLASH : 70us - 10ms + * 3. VCCQ : 70us - 10ms + * 4. VDDC : 30us - 100ms + * + * There is no feedback to know if the voltage has stabilized + * so this implementation will use the max ramp times. That + * means it adds significantly to the boot time. + */ +static void issd_power_sequence(void) +{ + struct gpio_seq { + int gpio; + int wait_ms; + } issd_gpio_seq[] = { + { 49, 100 }, /* VCC_IO: GPIO 49, wait 100ms */ + { 44, 10 }, /* VCC_FLASH: GPIO 44, wait 10ms */ + { 17, 10 }, /* VCCQ: GPIO 17, wait 10ms */ + { 16, 100 }, /* VDDC: GPIO 16, wait 100ms */ + }; + int step; + + for (step = 0; step < ARRAY_SIZE(issd_gpio_seq); step++) { + set_gpio(issd_gpio_seq[step].gpio, 1); + udelay(issd_gpio_seq[step].wait_ms * 1000); + } +} + void mainboard_romstage_entry(unsigned long bist) { struct pei_data pei_data = { @@ -119,4 +154,7 @@ void mainboard_romstage_entry(unsigned long bist) /* Call into the real romstage main with this board's attributes. */ romstage_common(&romstage_params); + + /* Power sequence the iSSD module */ + issd_power_sequence(); } |