diff options
| -rw-r--r-- | src/cpu/intel/haswell/romstage.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/early_init.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/haswell.h | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 4b563014e9..381d7bfcb5 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -25,7 +25,7 @@ void romstage_common(const struct romstage_params *params) /* Perform some early chipset initialization required * before RAM initialization can work */ - haswell_early_initialization(HASWELL_MOBILE); + haswell_early_initialization(); printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n"); if (wake_from_s3) { diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index fd188a1af0..9db6a9d0de 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -176,7 +176,7 @@ static void haswell_setup_iommu(void) reg32 | DMAR_LCKDN | GLBIOTLBINV | GLBCTXTINV); } -void haswell_early_initialization(int chipset_type) +void haswell_early_initialization(void) { /* Setup all BARs required for early PCIe and raminit */ haswell_setup_bars(); diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index bd441685b7..c3930493da 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -189,7 +189,7 @@ void intel_northbridge_haswell_finalize_smm(void); -void haswell_early_initialization(int chipset_type); +void haswell_early_initialization(void); void haswell_late_initialization(void); void set_translation_table(int start, int end, u64 base, int inc); void haswell_unhide_peg(void); |