diff options
| -rw-r--r-- | src/superio/ite/common/early_serial.c | 16 | ||||
| -rw-r--r-- | src/superio/ite/common/ite.h | 1 |
2 files changed, 17 insertions, 0 deletions
diff --git a/src/superio/ite/common/early_serial.c b/src/superio/ite/common/early_serial.c index b8a6ba558c..ec218a6c90 100644 --- a/src/superio/ite/common/early_serial.c +++ b/src/superio/ite/common/early_serial.c @@ -15,6 +15,7 @@ #define ITE_CONFIG_REG_WATCHDOG 0x72 /* watchdog config */ #define ITE_CONFIG_REG_WDT_TIMEOUT_LSB 0x73 /* watchdog timeout (LSB) */ #define ITE_CONFIG_REG_WDT_TIMEOUT_MSB 0x74 /* watchdog timeout (MSB) */ +#define ITE_CONFIG_REG_APC_PME_CTL1 0xf2 /* APC_PME Control 1 */ #define ITE_CONFIG_REG_APC_PME_CTL2 0xf4 /* APC_PME Control 2 */ /* Helper procedure */ @@ -143,6 +144,21 @@ void ite_kill_watchdog(pnp_devfn_t dev) } /* + * Disable PME# Output + * pass EC_DEV + */ +void ite_disable_pme_out(pnp_devfn_t dev) +{ + u8 tmp; + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + tmp = pnp_read_config(dev, ITE_CONFIG_REG_APC_PME_CTL1); + tmp |= 0x40; + pnp_write_config(dev, ITE_CONFIG_REG_APC_PME_CTL1, tmp); + pnp_exit_conf_state(dev); +} + +/* * Set AC resume to be up to the Southbridge * pass EC_DEV */ diff --git a/src/superio/ite/common/ite.h b/src/superio/ite/common/ite.h index 1a147bef65..8a1ab588cc 100644 --- a/src/superio/ite/common/ite.h +++ b/src/superio/ite/common/ite.h @@ -18,6 +18,7 @@ void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value); void ite_set_3vsbsw(pnp_devfn_t dev, bool enable); void ite_delay_pwrgd3(pnp_devfn_t dev); void ite_kill_watchdog(pnp_devfn_t dev); +void ite_disable_pme_out(pnp_devfn_t dev); void ite_ac_resume_southbridge(pnp_devfn_t dev); /* Alias for backwards compatibility */ |