diff options
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 27 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/Makefile.inc | 6 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/bootblock/bootblock.c | 6 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/bootblock/cache_as_ram.S | 152 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/bootblock.h | 6 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/placeholders.c | 8 |
6 files changed, 205 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index ca38494d79..e39fc9c25f 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS # Misc options + select C_ENVIRONMENT_BOOTBLOCK select COLLECT_TIMESTAMPS select HAVE_INTEL_FIRMWARE select MMCONF_SUPPORT @@ -32,6 +33,32 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select UDELAY_TSC +config MMCONF_BASE_ADDRESS + hex "PCI MMIO Base Address" + default 0xe0000000 + +config IOSF_BASE_ADDRESS + hex "MMIO Base Address of sideband bus" + default 0xd0000000 + +config DCACHE_RAM_BASE + hex "Base address of cache-as-RAM" + default 0xfef00000 + +config DCACHE_RAM_SIZE + hex "Length in bytes of cache-as-RAM" + default 0x80000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. + +config DCACHE_BSP_STACK_SIZE + hex + default 0x4000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + config CPU_ADDR_BITS int default 36 diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index b37cf8d8b3..b429b29ef8 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -7,8 +7,14 @@ subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc +bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock/cache_as_ram.S +bootblock-y += placeholders.c + romstage-y += placeholders.c smm-y += placeholders.c ramstage-y += placeholders.c +CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include + endif diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c new file mode 100644 index 0000000000..dc0b183bba --- /dev/null +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -0,0 +1,6 @@ +#include <soc/bootblock.h> +#include <arch/cpu.h> + +void asmlinkage bootblock_c_entry(void) +{ +} diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S new file mode 100644 index 0000000000..c81fe0a8e3 --- /dev/null +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -0,0 +1,152 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <device/pci_def.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/cr.h> +#include <cpu/x86/post_code.h> + +#define EVICT_CTL_MSR 0x2e0 + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: + /* + * eax: BIST value + */ + movd %eax, %mm2 + +.global cache_as_ram +cache_as_ram: + post_code(0x21) + + /* Clear/disable fixed MTRRs */ + mov $fixed_mtrr_list_size, %ebx + xor %eax, %eax + xor %edx, %edx +clear_fixed_mtrr: + add $-2, %ebx + movzwl fixed_mtrr_list(%ebx), %ecx + wrmsr + jnz clear_fixed_mtrr + + post_code(0x22) + + /* Figure put how many MTRRs we have, and clear them out */ + mov $MTRR_CAP_MSR, %ecx + rdmsr + movzb %al, %ebx /* Number of variable MTRRs */ + mov $MTRR_PHYS_BASE(0), %ecx + xor %eax, %eax + xor %edx, %edx + +clear_var_mtrr: + wrmsr + inc %ecx + wrmsr + inc %ecx + dec %ebx + jnz clear_var_mtrr + + post_code(0x23) + + /* Configure default memory type to uncacheable (UC) */ + mov $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + and $MTRR_DEF_TYPE_MASK, %eax + wrmsr + + post_code(0x24) + + /* Configure CAR region as write-back (WB) */ + mov $MTRR_PHYS_BASE(0), %ecx + mov $CONFIG_DCACHE_RAM_BASE, %eax + or $MTRR_TYPE_WRBACK, %eax + xor %edx,%edx + wrmsr + + /* Configure the MTRR mask for the size region */ + mov $MTRR_PHYS_MASK(0), %ecx + mov $~(CONFIG_DCACHE_RAM_SIZE - 1), %eax /* size mask */ + or $MTRR_PHYS_MASK_VALID, %eax + wrmsr + + post_code(0x25) + + /* Enable variable MTRRs */ + mov $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + or $MTRR_DEF_TYPE_EN, %eax + wrmsr + + /* Enable caching */ + mov %cr0, %eax + and $~(CR0_CD | CR0_NW), %eax + invd + mov %eax, %cr0 + + /* Disable cache eviction (setup stage) */ + mov $EVICT_CTL_MSR, %ecx + rdmsr + or $0x1, %eax + wrmsr + + post_code(0x26) + + /* Clear the cache memory region. This will also fill up the cache */ + mov $CONFIG_DCACHE_RAM_BASE, %edi + mov $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx + xor %eax, %eax + rep stos %eax, %es:(%edi) + + post_code(0x27) + + /* Disable cache eviction (run stage) */ + mov $EVICT_CTL_MSR, %ecx + rdmsr + or $0x2, %eax + wrmsr + + post_code(0x28) + +car_init_done: + + /* Setup bootblock stack */ + mov $_car_stack_end, %esp + +before_carstage: + post_code(0x2b) + + /* We can call into C functions now */ + call bootblock_c_entry + + /* Never reached */ + +.halt_forever: + post_code(POST_DEAD_CODE) + hlt + jmp .halt_forever + +fixed_mtrr_list: + .word MTRR_FIX_64K_00000 + .word MTRR_FIX_16K_80000 + .word MTRR_FIX_16K_A0000 + .word MTRR_FIX_4K_C0000 + .word MTRR_FIX_4K_C8000 + .word MTRR_FIX_4K_D0000 + .word MTRR_FIX_4K_D8000 + .word MTRR_FIX_4K_E0000 + .word MTRR_FIX_4K_E8000 + .word MTRR_FIX_4K_F0000 + .word MTRR_FIX_4K_F8000 +fixed_mtrr_list_size = . - fixed_mtrr_list diff --git a/src/soc/intel/apollolake/include/soc/bootblock.h b/src/soc/intel/apollolake/include/soc/bootblock.h new file mode 100644 index 0000000000..933c7fecd4 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/bootblock.h @@ -0,0 +1,6 @@ +#ifndef _SOC_APOLLOLAKE_BOOTBLOCK_H_ +#define _SOC_APOLLOLAKE_BOOTBLOCK_H_ +#include <arch/cpu.h> + +void asmlinkage bootblock_c_entry(void); +#endif diff --git a/src/soc/intel/apollolake/placeholders.c b/src/soc/intel/apollolake/placeholders.c index cf0fe368fc..3a818eb1e3 100644 --- a/src/soc/intel/apollolake/placeholders.c +++ b/src/soc/intel/apollolake/placeholders.c @@ -1,5 +1,7 @@ #include <cbmem.h> #include <cpu/x86/smm.h> +#include <delay.h> +#include <rules.h> void *cbmem_top(void) { @@ -9,3 +11,9 @@ void *cbmem_top(void) void southbridge_smi_set_eos(void) { } + +#if ENV_BOOTBLOCK +void init_timer(void) +{ +} +#endif |