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-rw-r--r--src/mainboard/google/brya/variants/orisa/include/variant/gpio.h13
-rw-r--r--src/mainboard/google/brya/variants/orisa/overridetree.cb1
2 files changed, 13 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h b/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h
index 0848b4b970..c3623839de 100644
--- a/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h
+++ b/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h
@@ -3,9 +3,20 @@
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
-#include <baseboard/gpio.h>
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI GPE0_ESPI
+/* EC wake is EC_SOC_WAKE_ODL which is routed to GPP_F17 */
+#define GPE_EC_WAKE GPE0_DW2_17
/* WP signal to PCH */
#define GPIO_PCH_WP GPP_E3
+/* EC in RW or RO */
+#define GPIO_EC_IN_RW GPP_F18
+/* GPIO IRQ for tight timestamps, MKBP interrupts */
+#define EC_SYNC_IRQ GPD2_IRQ
+/* Used to gate SoC's SLP_S0# signal */
+#define GPIO_SLP_S0_GATE GPP_H18
#endif
diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb
index 600eb02422..832e0c91e6 100644
--- a/src/mainboard/google/brya/variants/orisa/overridetree.cb
+++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb
@@ -14,6 +14,7 @@ chip soc/intel/alderlake
# GPE configuration
register "pmc_gpe0_dw1" = "GPP_B"
+ register "pmc_gpe0_dw2" = "GPP_F"
# S0ix enable
register "s0ix_enable" = "1"