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-rw-r--r--src/soc/amd/phoenix/Kconfig1
-rw-r--r--src/soc/amd/phoenix/include/soc/xhci.h17
-rw-r--r--src/soc/amd/phoenix/xhci.c5
3 files changed, 21 insertions, 2 deletions
diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig
index 5d3adec5ff..64617f9f2e 100644
--- a/src/soc/amd/phoenix/Kconfig
+++ b/src/soc/amd/phoenix/Kconfig
@@ -74,6 +74,7 @@ config SOC_AMD_PHOENIX
select SOC_AMD_COMMON_BLOCK_TSC
select SOC_AMD_COMMON_BLOCK_UART
select SOC_AMD_COMMON_BLOCK_UCODE
+ select SOC_AMD_COMMON_BLOCK_XHCI
select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB # TODO: Check if this is still correct
select SOC_AMD_COMMON_FSP_DMI_TABLES # TODO: Check if this is still correct
select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct
diff --git a/src/soc/amd/phoenix/include/soc/xhci.h b/src/soc/amd/phoenix/include/soc/xhci.h
new file mode 100644
index 0000000000..ec71ecef20
--- /dev/null
+++ b/src/soc/amd/phoenix/include/soc/xhci.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_PHOENIX_XHCI_H
+#define AMD_PHOENIX_XHCI_H
+
+#include <device/device.h>
+
+#define SOC_XHCI_0 DEV_PTR(xhci_0)
+#define SOC_XHCI_1 DEV_PTR(xhci_1)
+#define SOC_XHCI_2 NULL
+#define SOC_XHCI_3 NULL
+#define SOC_XHCI_4 NULL
+#define SOC_XHCI_5 NULL
+#define SOC_XHCI_6 NULL
+#define SOC_XHCI_7 NULL
+
+#endif /* AMD_PHOENIX_XHCI_H */
diff --git a/src/soc/amd/phoenix/xhci.c b/src/soc/amd/phoenix/xhci.c
index 06481edce2..8bb446f9f9 100644
--- a/src/soc/amd/phoenix/xhci.c
+++ b/src/soc/amd/phoenix/xhci.c
@@ -4,6 +4,7 @@
#include <amdblocks/gpio.h>
#include <amdblocks/smi.h>
+#include <amdblocks/xhci.h>
#include <bootstate.h>
#include <device/device.h>
#include <device/pci_ids.h>
@@ -14,13 +15,13 @@
static const struct sci_source xhci_sci_sources[] = {
{
.scimap = SMITYPE_XHC0_PME,
- .gpe = GEVENT_31,
+ .gpe = XHCI_GEVENT,
.direction = SMI_SCI_LVL_HIGH,
.level = SMI_SCI_EDG
},
{
.scimap = SMITYPE_XHC1_PME,
- .gpe = GEVENT_31,
+ .gpe = XHCI_GEVENT,
.direction = SMI_SCI_LVL_HIGH,
.level = SMI_SCI_EDG
}