diff options
| -rw-r--r-- | src/mainboard/google/brya/variants/anahera/gpio.c | 5 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/anahera/overridetree.cb | 2 |
2 files changed, 6 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/anahera/gpio.c b/src/mainboard/google/brya/variants/anahera/gpio.c index 9344d4c0ad..e67de78a04 100644 --- a/src/mainboard/google/brya/variants/anahera/gpio.c +++ b/src/mainboard/google/brya/variants/anahera/gpio.c @@ -39,6 +39,8 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_D3, NONE), /* D5 : SRCCLKREQ0# ==> NC */ PAD_NC(GPP_D5, NONE), + /* D7 : SRCCLKREQ2# ==> NC */ + PAD_NC(GPP_D7, NONE), /* D13 : ISH_UART0_RXD ==> NC */ PAD_NC(GPP_D13, NONE), /* D14 : ISH_UART0_TXD ==> NC */ @@ -56,6 +58,9 @@ static const struct pad_config override_gpio_table[] = { PAD_NC(GPP_E3, NONE), /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), + /* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ PAD_CFG_GPO(GPP_E20, 1, DEEP), /* E23 : DDPA_CTRLDATA ==> NC */ diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index 79f7a974cb..ad6746ebe8 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -125,7 +125,7 @@ chip soc/intel/alderlake # Enable PCIE eMMC bridge 7 using clk 6 register "pch_pcie_rp[PCH_RP(7)]" = "{ .clk_src = 6, - .clk_req = 2, + .clk_req = 6, .flags = PCIE_RP_HOTPLUG | PCIE_RP_AER, }" end #PCIE7 EMMC |