diff options
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 114 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 14 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/bootblock.c | 18 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/chip.c | 5 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/psp_transfer.h | 9 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/romstage.c | 7 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/timer.c | 7 |
7 files changed, 174 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig new file mode 100644 index 0000000000..6900ad787a --- /dev/null +++ b/src/soc/amd/cezanne/Kconfig @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config SOC_AMD_CEZANNE + bool + help + AMD Cezanne support + +if SOC_AMD_CEZANNE + +config SOC_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 + select RESET_VECTOR_IN_RAM + select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK_NONCAR + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF + select NO_MONOTONIC_TIMER # TODO: replace + select UNKNOWN_TSC_RATE # TODO: replace + +config EARLY_RESERVED_DRAM_BASE + hex + default 0x2000000 + help + This variable defines the base address of the DRAM which is reserved + for usage by coreboot in early stages (i.e. before ramstage is up). + This memory gets reserved in BIOS tables to ensure that the OS does + not use it, thus preventing corruption of OS memory in case of S3 + resume. + +config EARLYRAM_BSP_STACK_SIZE + hex + default 0x1000 + +config PSP_APOB_DRAM_ADDRESS + hex + default 0x2001000 + help + Location in DRAM where the PSP will copy the AGESA PSP Output + Block. + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0x1600 + help + Increase this value if preram cbmem console is getting truncated + +config BOOTBLOCK_ADDR + hex + default 0x2030000 + help + Sets the address in DRAM where bootblock should be loaded. + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x10000 + help + Sets the size of the bootblock stage that should be loaded in DRAM. + This variable controls the DRAM allocation size in linker script + for bootblock stage. + +config X86_RESET_VECTOR + hex + depends on ARCH_X86 + default 0x203fff0 + help + Sets the reset vector within bootblock where x86 starts execution. + Reset vector is supposed to live at offset -0x10 from end of + bootblock i.e. BOOTBLOCK_ADDR + C_ENV_BOOTBLOCK_SIZE - 0x10. + +config ROMSTAGE_ADDR + hex + default 0x2040000 + help + Sets the address in DRAM where romstage should be loaded. + +config ROMSTAGE_SIZE + hex + default 0x80000 + help + Sets the size of DRAM allocation for romstage in linker script. + +config FSP_M_ADDR + hex + default 0x20C0000 + help + Sets the address in DRAM where FSP-M should be loaded. cbfstool + performs relocation of FSP-M to this address. + +config FSP_M_SIZE + hex + default 0x80000 + help + Sets the size of DRAM allocation for FSP-M in linker script. + +config RAMBASE + hex + default 0x10000000 + +config CPU_ADDR_BITS + int + default 48 + +config MMCONF_BASE_ADDRESS + hex + default 0xF8000000 + +config MMCONF_BUS_NUMBER + int + default 64 + +endif # SOC_AMD_CEZANNE diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc new file mode 100644 index 0000000000..d1d8e97099 --- /dev/null +++ b/src/soc/amd/cezanne/Makefile.inc @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: BSD-3-Clause + +ifeq ($(CONFIG_SOC_AMD_CEZANNE),y) + +bootblock-y += bootblock.c + +romstage-y += romstage.c + +ramstage-y += chip.c +ramstage-y += timer.c + +CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include + +endif diff --git a/src/soc/amd/cezanne/bootblock.c b/src/soc/amd/cezanne/bootblock.c new file mode 100644 index 0000000000..3fd567720e --- /dev/null +++ b/src/soc/amd/cezanne/bootblock.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/amd_pci_mmconf.h> +#include <bootblock_common.h> +#include <stdint.h> + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + enable_pci_mmconf(); +} + +void bootblock_soc_early_init(void) +{ +} + +void bootblock_soc_init(void) +{ +} diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c new file mode 100644 index 0000000000..357d745b6b --- /dev/null +++ b/src/soc/amd/cezanne/chip.c @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> + +struct chip_operations soc_amd_cezanne_ops = { NULL }; diff --git a/src/soc/amd/cezanne/include/soc/psp_transfer.h b/src/soc/amd/cezanne/include/soc/psp_transfer.h new file mode 100644 index 0000000000..f5cd427d4c --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/psp_transfer.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_CEZANNE_PSP_TRANSFER_H +#define AMD_CEZANNE_PSP_TRANSFER_H + +#define TRANSFER_INFO_SIZE 64 +#define TIMESTAMP_BUFFER_SIZE 0x200 + +#endif /* AMD_CEZANNE_PSP_TRANSFER_H */ diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c new file mode 100644 index 0000000000..91074b2012 --- /dev/null +++ b/src/soc/amd/cezanne/romstage.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/cpu.h> + +asmlinkage void car_stage_entry(void) +{ +} diff --git a/src/soc/amd/cezanne/timer.c b/src/soc/amd/cezanne/timer.c new file mode 100644 index 0000000000..9054ffd972 --- /dev/null +++ b/src/soc/amd/cezanne/timer.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> + +void init_timer(void) +{ +} |