diff options
| -rw-r--r-- | src/drivers/intel/fsp2_0/memory_init.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index dcb44f6a18..4f0dbf6148 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -24,6 +24,10 @@ #include <types.h> #include <vb2_api.h> +#if CONFIG(SOC_INTEL_COMMON_BASECODE_TOM) +#include <intelbasecode/tom.h> +#endif + static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t)); static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) @@ -255,6 +259,12 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake) die_with_post_code(POST_INVALID_VENDOR_BINARY, "FSPM_ARCH_UPD not found!\n"); + /* Early caching of TOM region if valid mrc cache data is found */ +#if (CONFIG(SOC_INTEL_COMMON_BASECODE_TOM)) + if (arch_upd->NvsBufferPtr) + early_tom_enable_cache_range(); +#endif + /* Give SoC and mainboard a chance to update the UPD */ platform_fsp_memory_init_params_cb(&fspm_upd, fsp_version); |