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-rw-r--r--src/mainboard/google/brya/Kconfig2
-rw-r--r--src/mainboard/intel/adlrvp/Kconfig5
-rw-r--r--src/mainboard/intel/shadowmountain/Kconfig2
-rw-r--r--src/soc/intel/alderlake/Kconfig23
-rw-r--r--src/soc/intel/alderlake/include/soc/bootblock.h5
5 files changed, 26 insertions, 11 deletions
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index a5ca94209d..4b25af53aa 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -45,7 +45,7 @@ config BOARD_GOOGLE_BRYA_COMMON
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_I2C_TPM_CR50
select MAINBOARD_HAS_TPM2
- select SOC_INTEL_ALDERLAKE
+ select SOC_INTEL_ALDERLAKE_PCH_P
select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
select SOC_INTEL_CSE_LITE_SKU
select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED
diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig
index 2b78515776..657568502d 100644
--- a/src/mainboard/intel/adlrvp/Kconfig
+++ b/src/mainboard/intel/adlrvp/Kconfig
@@ -14,7 +14,6 @@ config BOARD_INTEL_ADLRVP_COMMON
select HAVE_ACPI_TABLES
select HAVE_SPD_IN_CBFS
select MAINBOARD_HAS_CHROMEOS
- select SOC_INTEL_ALDERLAKE
select SOC_INTEL_COMMON_BLOCK_IPU
select SOC_INTEL_CSE_LITE_SKU
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
@@ -23,11 +22,13 @@ config BOARD_INTEL_ADLRVP_P
select BOARD_INTEL_ADLRVP_COMMON
select DRIVERS_UART_8250IO
select MAINBOARD_USES_IFD_EC_REGION
+ select SOC_INTEL_ALDERLAKE_PCH_P
config BOARD_INTEL_ADLRVP_P_EXT_EC
select BOARD_INTEL_ADLRVP_COMMON
select DRIVERS_INTEL_PMC
select INTEL_LPSS_UART_FOR_CONSOLE
+ select SOC_INTEL_ALDERLAKE_PCH_P
config BOARD_INTEL_ADLRVP_P_MCHP
select BOARD_INTEL_ADLRVP_COMMON
@@ -36,7 +37,7 @@ config BOARD_INTEL_ADLRVP_P_MCHP
select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
select EC_GOOGLE_CHROMEEC_MEC
select INTEL_LPSS_UART_FOR_CONSOLE
- select SOC_INTEL_COMMON_BLOCK_IPU
+ select SOC_INTEL_ALDERLAKE_PCH_P
config BOARD_INTEL_ADLRVP_M
select BOARD_INTEL_ADLRVP_COMMON
diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig
index 553906a39c..9294857f0c 100644
--- a/src/mainboard/intel/shadowmountain/Kconfig
+++ b/src/mainboard/intel/shadowmountain/Kconfig
@@ -23,7 +23,7 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_SPI_TPM_CR50
select MAINBOARD_HAS_TPM2
select PCIEXP_HOTPLUG
- select SOC_INTEL_ALDERLAKE
+ select SOC_INTEL_ALDERLAKE_PCH_P
select SOC_INTEL_CSE_LITE_SKU
select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index e5d6d6b999..2f8f3da429 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -1,12 +1,21 @@
config SOC_INTEL_ALDERLAKE
bool
help
- Intel Alderlake support
+ Intel Alderlake support. Mainboards should specify the PCH
+ type using the `SOC_INTEL_ALDERLAKE_PCH_*` options instead
+ of selecting this option directly.
config SOC_INTEL_ALDERLAKE_PCH_M
bool
+ select SOC_INTEL_ALDERLAKE
help
- Choose this option if you have PCH-M chipset.
+ Choose this option if your mainboard has a PCH-M chipset.
+
+config SOC_INTEL_ALDERLAKE_PCH_P
+ bool
+ select SOC_INTEL_ALDERLAKE
+ help
+ Choose this option if your mainboard has a PCH-P chipset.
if SOC_INTEL_ALDERLAKE
@@ -169,12 +178,12 @@ endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
config MAX_PCH_ROOT_PORTS
int
default 10 if SOC_INTEL_ALDERLAKE_PCH_M
- default 12
+ default 12 if SOC_INTEL_ALDERLAKE_PCH_P
config MAX_CPU_ROOT_PORTS
int
default 1 if SOC_INTEL_ALDERLAKE_PCH_M
- default 3
+ default 3 if SOC_INTEL_ALDERLAKE_PCH_P
config MAX_ROOT_PORTS
int
@@ -183,12 +192,12 @@ config MAX_ROOT_PORTS
config MAX_PCIE_CLOCK_SRC
int
default 6 if SOC_INTEL_ALDERLAKE_PCH_M
- default 7
+ default 7 if SOC_INTEL_ALDERLAKE_PCH_P
config MAX_PCIE_CLOCK_REQ
int
- default 6 if SOC_INTEL_ALDERLAKE_PCH_M
- default 10
+ default 6 if SOC_INTEL_ALDERLAKE_PCH_M
+ default 10 if SOC_INTEL_ALDERLAKE_PCH_P
config SMM_TSEG_SIZE
hex
diff --git a/src/soc/intel/alderlake/include/soc/bootblock.h b/src/soc/intel/alderlake/include/soc/bootblock.h
index 0cf334fe09..059568d09b 100644
--- a/src/soc/intel/alderlake/include/soc/bootblock.h
+++ b/src/soc/intel/alderlake/include/soc/bootblock.h
@@ -3,6 +3,11 @@
#ifndef _SOC_ALDERLAKE_BOOTBLOCK_H_
#define _SOC_ALDERLAKE_BOOTBLOCK_H_
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_M) + \
+ CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) != 1
+#error "Please select exactly one PCH type"
+#endif
+
/* Bootblock pre console init programming */
void bootblock_pch_early_init(void);