diff options
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 5 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/sd.c | 37 |
4 files changed, 44 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 5f24ab0a5f..ee4fcbec78 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -59,6 +59,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_PMC select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 8dfff91544..194291e586 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -46,6 +46,7 @@ ramstage-y += systemagent.c ramstage-$(CONFIG_UART_DEBUG) += uart.c ramstage-$(CONFIG_UART_DEBUG) += uart_pch.c ramstage-y += vr_config.c +ramstage-y += sd.c smm-y += gpio.c smm-y += pmutil.c diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index dbe211da35..9117d13ed6 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -21,6 +21,8 @@ #include <intelblocks/gspi.h> #include <stdint.h> #include <soc/pch.h> +#include <soc/gpio_defs.h> +#include <soc/pci_devs.h> #include <soc/serialio.h> #include <soc/usb.h> #include <soc/vr_config.h> @@ -245,6 +247,9 @@ struct soc_intel_cannonlake_config { * PchSerialIoHidden */ uint8_t SerialIoDevMode[PchSerialIoIndexMAX]; + + /* GPIO SD card detect pin */ + unsigned int sdcard_cd_gpio; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/sd.c b/src/soc/intel/cannonlake/sd.c new file mode 100644 index 0000000000..2c0298fd78 --- /dev/null +++ b/src/soc/intel/cannonlake/sd.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/sd.h> +#include "chip.h" + +int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, struct device *dev) +{ + config_t *config = dev->chip_info; + + if (!config->sdcard_cd_gpio) + return -1; + + gpio->type = ACPI_GPIO_TYPE_INTERRUPT; + gpio->pull = ACPI_GPIO_PULL_NONE; + gpio->irq.mode = ACPI_IRQ_EDGE_TRIGGERED; + gpio->irq.polarity = ACPI_IRQ_ACTIVE_BOTH; + gpio->irq.shared = ACPI_IRQ_SHARED; + gpio->irq.wake = ACPI_IRQ_WAKE; + gpio->interrupt_debounce_timeout = 10000; /* 100ms */ + gpio->pin_count = 1; + gpio->pins[0] = config->sdcard_cd_gpio; + + return 0; +} |