diff options
| -rw-r--r-- | src/soc/intel/icelake/Kconfig | 5 | ||||
| -rw-r--r-- | src/soc/intel/icelake/chip.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/icelake/smihandler.c | 6 |
3 files changed, 5 insertions, 10 deletions
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 0a22549e9e..cee38c9d74 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -61,9 +61,12 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO - select HECI_DISABLE_USING_SMM select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI +config DISABLE_HECI1_AT_PRE_BOOT + default y if MAINBOARD_HAS_CHROMEOS + select HECI_DISABLE_USING_SMM + config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 9adc5b0565..05ec99c0b5 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -134,10 +134,6 @@ struct soc_intel_icelake_config { uint8_t Device4Enable; - /* HeciEnabled decides the state of Heci1 at end of boot - * Setting to 0 (default) disables Heci1 and hides the device from OS */ - uint8_t HeciEnabled; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index 2ca2816a20..5fb4f43378 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -16,11 +16,7 @@ */ void smihandler_soc_at_finalize(void) { - const struct soc_intel_icelake_config *config; - - config = config_of_soc(); - - if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) heci_disable(); } |