diff options
| -rw-r--r-- | src/soc/intel/meteorlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/acpi/pci_irqs.asl | 155 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/acpi/southbridge.asl | 3 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/chip.c | 17 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/fsp_params.c | 230 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/include/soc/irq.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/include/soc/pci_devs.h | 3 |
7 files changed, 249 insertions, 164 deletions
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 4d69566385..a612846ff0 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -67,6 +67,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_COMMON_BLOCK_IOE_P2SB + select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_MEMINIT select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_COMMON_BLOCK_PMC_EPOC diff --git a/src/soc/intel/meteorlake/acpi/pci_irqs.asl b/src/soc/intel/meteorlake/acpi/pci_irqs.asl deleted file mode 100644 index 70e9f3de6b..0000000000 --- a/src/soc/intel/meteorlake/acpi/pci_irqs.asl +++ /dev/null @@ -1,155 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -Name (PICP, Package () { - /* D31 */ - Package(){0x001FFFFF, 0, 0, 16 }, - Package(){0x001FFFFF, 1, 0, 17 }, - Package(){0x001FFFFF, 2, 0, 18 }, - Package(){0x001FFFFF, 3, 0, 19 }, - /* D30 */ - Package(){0x001EFFFF, 0, 0, 16 }, - Package(){0x001EFFFF, 1, 0, 17 }, - Package(){0x001EFFFF, 2, 0, 27 }, - Package(){0x001EFFFF, 3, 0, 28 }, - /* D28 */ - Package(){0x001CFFFF, 0, 0, 16 }, - Package(){0x001CFFFF, 1, 0, 17 }, - Package(){0x001CFFFF, 2, 0, 18 }, - Package(){0x001CFFFF, 3, 0, 19 }, - /* D25 */ - Package(){0x0019FFFF, 0, 0, 29 }, - Package(){0x0019FFFF, 1, 0, 30 }, - Package(){0x0019FFFF, 2, 0, 31 }, - /* D23 */ - Package(){0x0017FFFF, 0, 0, 16 }, - /* D22 */ - Package(){0x0016FFFF, 0, 0, 16 }, - Package(){0x0016FFFF, 1, 0, 17 }, - Package(){0x0016FFFF, 2, 0, 18 }, - Package(){0x0016FFFF, 3, 0, 19 }, - /* D21 */ - Package(){0x0015FFFF, 0, 0, 32 }, - Package(){0x0015FFFF, 1, 0, 33 }, - Package(){0x0015FFFF, 2, 0, 34 }, - Package(){0x0015FFFF, 3, 0, 35 }, - /* D20 */ - Package(){0x0014FFFF, 0, 0, 16 }, - Package(){0x0014FFFF, 1, 0, 17 }, - Package(){0x0014FFFF, 2, 0, 18 }, - /* D18 */ - Package(){0x0012FFFF, 0, 0, 26 }, - Package(){0x0012FFFF, 1, 0, 37 }, - Package(){0x0012FFFF, 2, 0, 25 }, - /* D16 */ - Package(){0x0010FFFF, 0, 0, 23 }, - Package(){0x0010FFFF, 1, 0, 22 }, - /* D13 */ - Package(){0x000DFFFF, 0, 0, 16 }, - Package(){0x000DFFFF, 1, 0, 17 }, - /* D11 */ - Package(){0x000BFFFF, 0, 0, 16 }, - /* D8 */ - Package(){0x0008FFFF, 0, 0, 16 }, - /* D7 */ - Package(){0x0007FFFF, 0, 0, 16 }, - Package(){0x0007FFFF, 1, 0, 17 }, - Package(){0x0007FFFF, 2, 0, 18 }, - Package(){0x0007FFFF, 3, 0, 19 }, - /* D6 */ - Package(){0x0006FFFF, 0, 0, 16 }, - Package(){0x0006FFFF, 1, 0, 17 }, - Package(){0x0006FFFF, 2, 0, 18 }, - Package(){0x0006FFFF, 3, 0, 19 }, - /* D5 */ - Package(){0x0005FFFF, 0, 0, 16 }, - /* D4 */ - Package(){0x0004FFFF, 0, 0, 16 }, - /* D2 */ - Package(){0x0002FFFF, 0, 0, 16 }, - /* D1 */ - Package(){0x0001FFFF, 0, 0, 16 }, - Package(){0x0001FFFF, 1, 0, 17 }, - Package(){0x0001FFFF, 2, 0, 18 }, - Package(){0x0001FFFF, 3, 0, 19 }, -}) - -Name (PICN, Package () { - /* D31 */ - Package(){0x001FFFFF, 0, 0, 11 }, - Package(){0x001FFFFF, 1, 0, 10 }, - Package(){0x001FFFFF, 2, 0, 11 }, - Package(){0x001FFFFF, 3, 0, 11 }, - /* D30 */ - Package(){0x001EFFFF, 0, 0, 11 }, - Package(){0x001EFFFF, 1, 0, 10 }, - Package(){0x001EFFFF, 2, 0, 11 }, - Package(){0x001EFFFF, 3, 0, 11 }, - /* D28 */ - Package(){0x001CFFFF, 0, 0, 11 }, - Package(){0x001CFFFF, 1, 0, 10 }, - Package(){0x001CFFFF, 2, 0, 11 }, - Package(){0x001CFFFF, 3, 0, 11 }, - /* D25 */ - Package(){0x0019FFFF, 0, 0, 11 }, - Package(){0x0019FFFF, 1, 0, 10 }, - Package(){0x0019FFFF, 2, 0, 11 }, - /* D23 */ - Package(){0x0017FFFF, 0, 0, 11 }, - /* D22 */ - Package(){0x0016FFFF, 0, 0, 11 }, - Package(){0x0016FFFF, 1, 0, 10 }, - Package(){0x0016FFFF, 2, 0, 11 }, - Package(){0x0016FFFF, 3, 0, 11 }, - /* D21 */ - Package(){0x0015FFFF, 0, 0, 11 }, - Package(){0x0015FFFF, 1, 0, 10 }, - Package(){0x0015FFFF, 2, 0, 11 }, - Package(){0x0015FFFF, 3, 0, 11 }, - /* D20 */ - Package(){0x0014FFFF, 0, 0, 11 }, - Package(){0x0014FFFF, 1, 0, 10 }, - Package(){0x0014FFFF, 2, 0, 11 }, - /* D18 */ - Package(){0x0012FFFF, 0, 0, 11 }, - Package(){0x0012FFFF, 1, 0, 10 }, - Package(){0x0012FFFF, 2, 0, 11 }, - /* D16 */ - Package(){0x0010FFFF, 0, 0, 11 }, - Package(){0x0010FFFF, 1, 0, 10 }, - /* D13 */ - Package(){0x000DFFFF, 0, 0, 11 }, - /* D11 */ - Package(){0x000BFFFF, 0, 0, 11 }, - /* D8 */ - Package(){0x0008FFFF, 0, 0, 11 }, - /* D7 */ - Package(){0x0007FFFF, 0, 0, 11 }, - Package(){0x0007FFFF, 1, 0, 10 }, - Package(){0x0007FFFF, 2, 0, 11 }, - Package(){0x0007FFFF, 3, 0, 11 }, - /* D6 */ - Package(){0x0006FFFF, 0, 0, 11 }, - Package(){0x0006FFFF, 1, 0, 10 }, - Package(){0x0006FFFF, 2, 0, 11 }, - Package(){0x0006FFFF, 3, 0, 11 }, - /* D5 */ - Package(){0x0005FFFF, 0, 0, 11 }, - /* D4 */ - Package(){0x0004FFFF, 0, 0, 11 }, - /* D2 */ - Package(){0x0002FFFF, 0, 0, 11 }, - /* D1 */ - Package(){0x0001FFFF, 0, 0, 11 }, - Package(){0x0001FFFF, 1, 0, 10 }, - Package(){0x0001FFFF, 2, 0, 11 }, - Package(){0x0001FFFF, 3, 0, 11 }, -}) - -Method (_PRT) -{ - If (PICM) { - Return (^PICP) - } Else { - Return (^PICN) - } -} diff --git a/src/soc/intel/meteorlake/acpi/southbridge.asl b/src/soc/intel/meteorlake/acpi/southbridge.asl index 448cbf56a1..6ecadbbd29 100644 --- a/src/soc/intel/meteorlake/acpi/southbridge.asl +++ b/src/soc/intel/meteorlake/acpi/southbridge.asl @@ -5,9 +5,6 @@ #include <soc/itss.h> #include <soc/pcr_ids.h> -/* PCI IRQ assignment */ -#include "pci_irqs.asl" - /* PCR access */ #include <soc/intel/common/acpi/pcr.asl> diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c index 041b16d413..332c0f8ce0 100644 --- a/src/soc/intel/meteorlake/chip.c +++ b/src/soc/intel/meteorlake/chip.c @@ -7,6 +7,7 @@ #include <intelblocks/acpi.h> #include <intelblocks/cfg.h> #include <intelblocks/gpio.h> +#include <intelblocks/irq.h> #include <intelblocks/itss.h> #include <intelblocks/p2sb.h> #include <intelblocks/pcie_rp.h> @@ -151,6 +152,19 @@ void soc_init_pre_device(void *chip_info) pcie_rp_update_devicetree(get_pcie_rp_table()); } +static void cpu_fill_ssdt(const struct device *dev) +{ + if (!generate_pin_irq_map()) + printk(BIOS_ERR, "Failed to generate ACPI _PRT table!\n"); + + generate_cpu_entries(dev); +} + +static void cpu_set_north_irqs(struct device *dev) +{ + irq_program_non_pch(); +} + static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, @@ -164,8 +178,9 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, + .enable_resources = cpu_set_north_irqs, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_fill_ssdt = generate_cpu_entries, + .acpi_fill_ssdt = cpu_fill_ssdt, #endif }; diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index d40779ab79..0cf221bd84 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -13,6 +13,7 @@ #include <fsp/util.h> #include <option.h> #include <intelblocks/cse.h> +#include <intelblocks/irq.h> #include <intelblocks/lpss.h> #include <intelblocks/mp_init.h> #include <intelblocks/systemagent.h> @@ -27,6 +28,7 @@ #include <soc/ramstage.h> #include <soc/soc_chip.h> #include <soc/soc_info.h> +#include <stdlib.h> #include <string.h> #include <types.h> @@ -39,6 +41,219 @@ #define DEF_DMVAL 15 #define DEF_DITOVAL 625 +static const struct slot_irq_constraints irq_constraints[] = { + { + .slot = PCI_DEV_SLOT_PCIE_3, + .fns = { + FIXED_INT_PIRQ(PCI_DEVFN_PCIE12, PCI_INT_A, PIRQ_A), + }, + }, + { + .slot = PCI_DEV_SLOT_IGD, + .fns = { + /* INTERRUPT_PIN is RO/0x01 */ + FIXED_INT_ANY_PIRQ(PCI_DEV_SLOT_IGD, PCI_INT_A), + }, + }, + { + .slot = PCI_DEV_SLOT_DPTF, + .fns = { + ANY_PIRQ(PCI_DEVFN_DPTF), + }, + }, + { + .slot = PCI_DEV_SLOT_IPU, + .fns = { + /* INTERRUPT_PIN is RO/0x01, and INTERRUPT_LINE is RW, + but S0ix fails when not set to 16 (b/193434192) */ + FIXED_INT_PIRQ(PCI_DEVFN_IPU, PCI_INT_A, PIRQ_A), + }, + }, + { + .slot = PCI_DEV_SLOT_PCIE_2, + .fns = { + FIXED_INT_PIRQ(PCI_DEVFN_PCIE9, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE10, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE11, PCI_INT_C, PIRQ_C), + }, + }, + { + .slot = PCI_DEV_SLOT_TBT, + .fns = { + ANY_PIRQ(PCI_DEVFN_TBT0), + ANY_PIRQ(PCI_DEVFN_TBT1), + ANY_PIRQ(PCI_DEVFN_TBT2), + ANY_PIRQ(PCI_DEVFN_TBT3), + }, + }, + { + .slot = PCI_DEV_SLOT_GNA, + .fns = { + /* INTERRUPT_PIN is RO/0x01 */ + FIXED_INT_ANY_PIRQ(PCI_DEVFN_GNA, PCI_INT_A), + }, + }, + { + .slot = PCI_DEV_SLOT_VPU, + .fns = { + /* INTERRUPT_PIN is RO/0x01 */ + FIXED_INT_ANY_PIRQ(PCI_DEVFN_VPU, PCI_INT_A), + }, + }, + { + .slot = PCI_DEV_SLOT_TCSS, + .fns = { + ANY_PIRQ(PCI_DEVFN_TCSS_XHCI), + ANY_PIRQ(PCI_DEVFN_TCSS_XDCI), + }, + }, + { + .slot = PCI_DEV_SLOT_THC, + .fns = { + ANY_PIRQ(PCI_DEVFN_THC0), + ANY_PIRQ(PCI_DEVFN_THC1), + }, + }, + { + .slot = PCI_DEV_SLOT_ISH, + .fns = { + DIRECT_IRQ(PCI_DEVFN_ISH), + DIRECT_IRQ(PCI_DEVFN_GSPI2), + ANY_PIRQ(PCI_DEVFN_UFS), + }, + }, + { + .slot = PCI_DEV_SLOT_XHCI, + .fns = { + ANY_PIRQ(PCI_DEVFN_XHCI), + DIRECT_IRQ(PCI_DEVFN_USBOTG), + ANY_PIRQ(PCI_DEVFN_CNVI_WIFI), + }, + }, + { + .slot = PCI_DEV_SLOT_SIO0, + .fns = { + DIRECT_IRQ(PCI_DEVFN_I2C0), + DIRECT_IRQ(PCI_DEVFN_I2C1), + DIRECT_IRQ(PCI_DEVFN_I2C2), + DIRECT_IRQ(PCI_DEVFN_I2C3), + }, + }, + { + .slot = PCI_DEV_SLOT_CSE, + .fns = { + ANY_PIRQ(PCI_DEVFN_CSE), + ANY_PIRQ(PCI_DEVFN_CSE_2), + ANY_PIRQ(PCI_DEVFN_CSE_IDER), + ANY_PIRQ(PCI_DEVFN_CSE_KT), + ANY_PIRQ(PCI_DEVFN_CSE_3), + ANY_PIRQ(PCI_DEVFN_CSE_4), + }, + }, + { + .slot = PCI_DEV_SLOT_SATA, + .fns = { + ANY_PIRQ(PCI_DEVFN_SATA), + }, + }, + { + .slot = PCI_DEV_SLOT_SIO1, + .fns = { + DIRECT_IRQ(PCI_DEVFN_I2C4), + DIRECT_IRQ(PCI_DEVFN_I2C5), + DIRECT_IRQ(PCI_DEVFN_UART2), + }, + }, + { + .slot = PCI_DEV_SLOT_PCIE_1, + .fns = { + FIXED_INT_PIRQ(PCI_DEVFN_PCIE1, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE2, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE3, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE4, PCI_INT_D, PIRQ_D), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE5, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE6, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE7, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(PCI_DEVFN_PCIE8, PCI_INT_D, PIRQ_D), + }, + }, + { + .slot = PCI_DEV_SLOT_SIO2, + .fns = { + /* UART0 shares an interrupt line with TSN0, so must use + a PIRQ */ + FIXED_INT_ANY_PIRQ(PCI_DEVFN_UART0, PCI_INT_A), + /* UART1 shares an interrupt line with TSN1, so must use + a PIRQ */ + FIXED_INT_ANY_PIRQ(PCI_DEVFN_UART1, PCI_INT_B), + DIRECT_IRQ(PCI_DEVFN_GSPI0), + DIRECT_IRQ(PCI_DEVFN_GSPI1), + }, + }, + { + .slot = PCI_DEV_SLOT_ESPI, + .fns = { + ANY_PIRQ(PCI_DEVFN_HDA), + ANY_PIRQ(PCI_DEVFN_SMBUS), + ANY_PIRQ(PCI_DEVFN_GBE), + /* INTERRUPT_PIN is RO/0x01 */ + FIXED_INT_ANY_PIRQ(PCI_DEVFN_NPK, PCI_INT_A), + }, + }, +}; + +bool is_pch_slot(unsigned int devfn) +{ + if (PCI_SLOT(devfn) >= MIN_PCH_SLOT) + return true; + const struct pcie_rp_group *group; + for (group = get_pcie_rp_table(); group->count; ++group) { + if (PCI_SLOT(devfn) == group->slot) + return true; + } + return false; +} + +static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count) +{ + const struct pci_irq_entry *entry = get_cached_pci_irqs(); + SI_PCH_DEVICE_INTERRUPT_CONFIG *config; + size_t pch_total = 0; + size_t cfg_count = 0; + + if (!entry) + return NULL; + + /* Count PCH devices */ + while (entry) { + if (is_pch_slot(entry->devfn)) + ++pch_total; + entry = entry->next; + } + + /* Convert PCH device entries to FSP format */ + config = calloc(pch_total, sizeof(*config)); + entry = get_cached_pci_irqs(); + while (entry) { + if (!is_pch_slot(entry->devfn)) { + entry = entry->next; + continue; + } + + config[cfg_count].Device = PCI_SLOT(entry->devfn); + config[cfg_count].Function = PCI_FUNC(entry->devfn); + config[cfg_count].IntX = (SI_PCH_INT_PIN)entry->pin; + config[cfg_count].Irq = entry->irq; + ++cfg_count; + + entry = entry->next; + } + + *out_count = cfg_count; + + return config; +} + /* * ME End of Post configuration * 0 - Disable EOP. @@ -442,6 +657,20 @@ static void fill_fsps_ai_params(FSP_S_CONFIG *s_cfg, s_cfg->VpuEnable = is_devfn_enabled(PCI_DEVFN_VPU); } +static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_meteorlake_config *config) +{ + if (!assign_pci_irqs(irq_constraints, ARRAY_SIZE(irq_constraints))) + die("ERROR: Unable to assign PCI IRQs, and no _PRT table available\n"); + + size_t pch_count = 0; + const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count); + + s_cfg->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs); + s_cfg->NumOfDevIntConfig = pch_count; + printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n"); +} + static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg) { /* @@ -484,6 +713,7 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, fill_fsps_misc_power_params, fill_fsps_ufs_params, fill_fsps_ai_params, + fill_fsps_irq_params, }; for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++) diff --git a/src/soc/intel/meteorlake/include/soc/irq.h b/src/soc/intel/meteorlake/include/soc/irq.h index edc09a1332..59727a68ca 100644 --- a/src/soc/intel/meteorlake/include/soc/irq.h +++ b/src/soc/intel/meteorlake/include/soc/irq.h @@ -9,8 +9,4 @@ #define PCH_IRQ10 10 #define PCH_IRQ11 11 -#define LPSS_UART0_IRQ 16 -#define LPSS_UART1_IRQ 17 -#define LPSS_UART2_IRQ 31 - #endif diff --git a/src/soc/intel/meteorlake/include/soc/pci_devs.h b/src/soc/intel/meteorlake/include/soc/pci_devs.h index 9cea98ef65..5c584b09dd 100644 --- a/src/soc/intel/meteorlake/include/soc/pci_devs.h +++ b/src/soc/intel/meteorlake/include/soc/pci_devs.h @@ -221,7 +221,8 @@ #endif /* for common code */ -#define PCH_DEV_SLOT_CSE PCI_DEV_SLOT_CSE +#define MIN_PCH_SLOT PCI_DEV_SLOT_THC +#define PCH_DEV_SLOT_CSE PCI_DEV_SLOT_CSE #define PCH_DEVFN_CSE PCI_DEVFN_CSE #define PCH_DEV_CSE PCI_DEV_CSE #define PCH_DEV_SPI PCI_DEV_SPI |