diff options
| -rwxr-xr-x | Documentation/soc/amd/family17h.md | 45 | ||||
| -rw-r--r-- | src/soc/amd/picasso/Kconfig | 30 | ||||
| -rw-r--r-- | src/soc/amd/picasso/Makefile.inc | 72 |
3 files changed, 97 insertions, 50 deletions
diff --git a/Documentation/soc/amd/family17h.md b/Documentation/soc/amd/family17h.md index b917c94526..23088cd12b 100755 --- a/Documentation/soc/amd/family17h.md +++ b/Documentation/soc/amd/family17h.md @@ -237,6 +237,51 @@ Picasso's FSP is compatible with rev. 2.0 of the External Architecture Specification. Deviations, e.g., no FSP-T support, shall be published in an Integration Guide. +## APCB setup + +APCBs are used to provide the PSP with SPD information and optionally a set of +GPIOs to use for selecting which SPD to load. + +### Prebuilt +The picasso `Makefile` expects APCBs to be located in +`3rdparty/blobs/mainboard/$(MAINBOARDDIR)`. If you have a pre-built binary just +add the following to your mainboard's Makefile. + +``` +# i.e., 3rdparty/blobs/mainboard/amd/mandolin/APCB_mandolin.bin +APCB_SOURCES = mandolin +``` + +### Generating APCBs +If you have a template APCB file, the `apcb_edit` tool can be used to inject the +SPD and GPIOs used to select the correct slot. Entries should match this +pattern `{NAME}_x{1,2}`. There should be a matching SPD hex file in +`SPD_SOURCES_DIR` matching the pattern `{NAME}.spd.hex`. +The `_x{1,2}` suffix denotes single or dual channel. Up to 16 slots can be used. +If a slot is empty, the special empty keyword can be used. This will generate +an APCB with an empty SPD. + +``` +APCB_SOURCES = hynix-HMA851S6CJR6N-VK_x1 # 0b0000 +APCB_SOURCES += hynix-HMAA1GS6CMR6N-VK_x2 # 0b0001 +APCB_SOURCES += empty # 0b0010 +APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0011 +``` + +#### APCB Board ID GPIO configuration. +The GPIOs determine which memory SPD will be used during boot. +``` +# APCB_BOARD_ID_GPIO[0-3] = GPIO_NUMBER GPIO_IO_MUX GPIO_BANK_CTL +# GPIO_NUMBER: FCH GPIO number +# GPIO_IO_MUX: Value write to IOMUX to configure this GPIO +# GPIO_BANK_CTL: Value write to GPIOBankCtl[23:16] to configure this GPIO + +APCB_BOARD_ID_GPIO0 = 121 1 0 +APCB_BOARD_ID_GPIO1 = 120 1 0 +APCB_BOARD_ID_GPIO2 = 131 3 0 +APCB_BOARD_ID_GPIO3 = 116 1 0 +``` + ## Footnotes 1. *AMD Platform Security Processor BIOS Architecture Design Guide diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 7173b6c06f..48e1cc2e6b 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -299,36 +299,6 @@ config AMD_PUBKEY_FILE string default "3rdparty/amd_blobs/picasso/PSP/AmdPubKeyRV.bin" -config PSP_APCB_FILE - string - help - The name of the AGESA Parameter Customization Block. This image is - instance ID 0 in the PSP's BIOS Directory Table. - -config PSP_APCB1_FILE - string - help - If specified, this image is instance ID 1 in the PSP's BIOS - Directory Table. - -config PSP_APCB2_FILE - string - help - If specified, this image is instance ID 2 in the PSP's BIOS - Directory Table. - -config PSP_APCB3_FILE - string - help - If specified, this image is instance ID 3 in the PSP's BIOS - Directory Table. - -config PSP_APCB4_FILE - string - help - If specified, this image is instance ID 4 in the PSP's BIOS - Directory Table. - config PSP_APOB_DESTINATION hex default 0x9f00000 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index a82a227c15..6fc834e56b 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -78,6 +78,8 @@ CPPFLAGS_common += -I$(src)/soc/amd/picasso/include CPPFLAGS_common += -I$(src)/soc/amd/picasso/acpi CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/picasso +MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR) + # ROMSIG Normally At ROMBASE + 0x20000 # Overridden by CONFIG_AMD_FWM_POSITION_INDEX # +-----------+---------------+----------------+------------+ @@ -175,11 +177,7 @@ endif # # type = 0x60 -PSP_APCB0_FILE=$(call strip_quotes, $(CONFIG_PSP_APCB_FILE)) -PSP_APCB1_FILE=$(call strip_quotes, $(CONFIG_PSP_APCB1_FILE)) -PSP_APCB2_FILE=$(call strip_quotes, $(CONFIG_PSP_APCB2_FILE)) -PSP_APCB3_FILE=$(call strip_quotes, $(CONFIG_PSP_APCB3_FILE)) -PSP_APCB4_FILE=$(call strip_quotes, $(CONFIG_PSP_APCB4_FILE)) +PSP_APCB_FILES=$(foreach f, $(APCB_SOURCES), $(obj)/APCB_$(f).bin) # type = 0x61 PSP_APOB_BASE=$(CONFIG_PSP_APOB_DESTINATION) @@ -257,11 +255,10 @@ OPT_ABL6_FILE=$(call add_opt_prefix, $(PSP_ABL6_FILE), --abl-image) OPT_ABL7_FILE=$(call add_opt_prefix, $(PSP_ABL7_FILE), --abl-image) OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) -OPT_PSP_APCB0_FILE=$(call add_opt_prefix, $(PSP_APCB0_FILE), --instance 0 --apcb) -OPT_PSP_APCB1_FILE=$(call add_opt_prefix, $(PSP_APCB1_FILE), --instance 1 --apcb) -OPT_PSP_APCB2_FILE=$(call add_opt_prefix, $(PSP_APCB2_FILE), --instance 2 --apcb) -OPT_PSP_APCB3_FILE=$(call add_opt_prefix, $(PSP_APCB3_FILE), --instance 3 --apcb) -OPT_PSP_APCB4_FILE=$(call add_opt_prefix, $(PSP_APCB4_FILE), --instance 4 --apcb) +OPT_PSP_APCB_FILES=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \ + $(call add_opt_prefix, $(word $(i), $(PSP_APCB_FILES)), \ + --instance $(shell printf "%x" $$(($(i)-1))) --apcb )) + OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) @@ -281,15 +278,53 @@ OPT_PSP_UCODE_FILE2=$(call add_opt_prefix, $(PSP_UCODE_FILE2), --instance 1 --uc OPT_PSP_UCODE_FILE3=$(call add_opt_prefix, $(PSP_UCODE_FILE3), --instance 2 --ucode) OPT_MP2CFG_FILE=$(call add_opt_prefix, $(PSP_MP2CFG_FILE), --mp2-config) +# Copy prebuild APCBs if they exist +$(obj)/APCB_%.bin: $(MAINBOARD_BLOBS_DIR)/APCB_%.bin + cp $< $@ + +# APCB binary with magic numbers to be replaced by apcb_edit tool +APCB_MAGIC_BLOB:=$(MAINBOARD_BLOBS_DIR)/APCB_magic.bin + +$(obj)/APCB_empty.bin: $(APCB_MAGIC_BLOB) $(APCB_EDIT_TOOL) + $(APCB_EDIT_TOOL) \ + $(APCB_MAGIC_BLOB) \ + $@ \ + --board_id_gpio0 $(APCB_BOARD_ID_GPIO0) \ + --board_id_gpio1 $(APCB_BOARD_ID_GPIO1) \ + --board_id_gpio2 $(APCB_BOARD_ID_GPIO2) \ + --board_id_gpio3 $(APCB_BOARD_ID_GPIO3) + +$(obj)/APCB_%_x1.bin: $$(SPD_SOURCES_DIR)/%.spd.hex \ + $(APCB_EDIT_TOOL) \ + $(APCB_MAGIC_BLOB) + $(APCB_EDIT_TOOL) \ + $(APCB_MAGIC_BLOB) \ + $@ \ + --hex \ + --spd_0_0 $< \ + --board_id_gpio0 $(APCB_BOARD_ID_GPIO0) \ + --board_id_gpio1 $(APCB_BOARD_ID_GPIO1) \ + --board_id_gpio2 $(APCB_BOARD_ID_GPIO2) \ + --board_id_gpio3 $(APCB_BOARD_ID_GPIO3) + +$(obj)/APCB_%_x2.bin: $$(SPD_SOURCES_DIR)/%.spd.hex \ + $(APCB_EDIT_TOOL) \ + $(APCB_MAGIC_BLOB) + $(APCB_EDIT_TOOL) \ + $(APCB_MAGIC_BLOB) \ + $@ \ + --hex \ + --spd_0_0 $< \ + --spd_1_0 $< \ + --board_id_gpio0 $(APCB_BOARD_ID_GPIO0) \ + --board_id_gpio1 $(APCB_BOARD_ID_GPIO1) \ + --board_id_gpio2 $(APCB_BOARD_ID_GPIO2) \ + --board_id_gpio3 $(APCB_BOARD_ID_GPIO3) + $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PSPBTLDR_FILE)) \ $(call strip_quotes, $(PSPSCUREOS_FILE)) \ $(call strip_quotes, $(PSP_SEC_DBG_KEY_FILE)) \ - $(call strip_quotes, $(PSP_APCB0_FILE)) \ - $(call strip_quotes, $(PSP_APCB1_FILE)) \ - $(call strip_quotes, $(PSP_APCB2_FILE)) \ - $(call strip_quotes, $(PSP_APCB3_FILE)) \ - $(call strip_quotes, $(PSP_APCB4_FILE)) \ $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ $(call strip_quotes, $(PSP_PMUI_FILE1)) \ $(call strip_quotes, $(PSP_PMUI_FILE2)) \ @@ -322,6 +357,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call_strip_quotes, $(PSP_S0I3_FILE)) \ $(call_strip_quotes, $(PSP_IKEK_FILE)) \ $(call_strip_quotes, $(PSP_SEC_DEBUG_FILE)) \ + $$(PSP_APCB_FILES) \ $(AMDFWTOOL) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" @@ -334,11 +370,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(OPT_SMUFW2_SUB2_FILE) \ $(OPT_SMUFW1_SUB1_FILE) \ $(OPT_SMUFW2_SUB1_FILE) \ - $(OPT_PSP_APCB0_FILE) \ - $(OPT_PSP_APCB1_FILE) \ - $(OPT_PSP_APCB2_FILE) \ - $(OPT_PSP_APCB3_FILE) \ - $(OPT_PSP_APCB4_FILE) \ + $(OPT_PSP_APCB_FILES) \ $(OPT_APOB_ADDR) \ $(OPT_APOBNV_ADDR) \ $(OPT_APOBNV_SIZE) \ |