diff options
| -rw-r--r-- | util/inteltool/inteltool.c | 6 | ||||
| -rw-r--r-- | util/inteltool/inteltool.h | 4 | ||||
| -rw-r--r-- | util/inteltool/memory.c | 8 | ||||
| -rw-r--r-- | util/inteltool/pcie.c | 4 |
4 files changed, 17 insertions, 5 deletions
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index dfe8ca6238..9a4ab89b9f 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -81,7 +81,11 @@ static const struct { /* Host bridges /DRAM controllers integrated in CPUs */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_0TH_GEN, "0th generation (Nehalem family) Core Processor" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D, + "1st generation (Westmere family) Core Processor" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_M, + "1st generation (Westmere family) Core Processor" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_0048, "1st generation (Westmere family) Core Processor" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D, "2nd generation (Sandy Bridge family) Core Processor (Desktop)" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 018e92fe26..9ed958c736 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -346,7 +346,9 @@ static inline uint32_t inl(unsigned port) /* Intel starts counting these generations with the integration of the DRAM controller */ #define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN 0xd132 /* Nehalem */ -#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */ +#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D 0x0040 /* Clarkdale (Westmere Desktop) */ +#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_M 0x0044 /* Arrandale (Westmere Mobile) */ +#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_0048 0x0048 /* Unknown Westmere */ #define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D 0x0100 /* Sandy Bridge (Desktop) */ #define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M 0x0104 /* Sandy Bridge (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3 0x0108 /* Sandy Bridge (Xeon E3) */ diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 2ae331a576..3e7d3d70b6 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -192,7 +192,9 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; break; - case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_0048: mchbar_phys = pci_read_long(nb, 0x48); mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; mchbar_phys &= 0x0000000fffffc000UL; /* 35:14 */ @@ -266,7 +268,9 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s switch (nb->device_id) { - case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_0048: printf ("clock_speed_index = %x\n", read_500 (0,0x609, 6) >> 1); dump_timings (); if (dump_spd_file != NULL) diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 7303811b67..32afa714fc 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -378,7 +378,9 @@ int print_dmibar(struct pci_dev *nb) dmi_registers = nehalem_dmi_registers; size = ARRAY_SIZE(nehalem_dmi_registers); break; - case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_M: + case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN_0048: dmibar_phys = pci_read_long(nb, 0x68); dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; dmibar_phys &= 0x0000000ffffff000UL; /* 35:12 */ |