diff options
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index a2d297dc79..84b965e605 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -115,6 +115,9 @@ chip soc/intel/tigerlake register "TcssXhciEn" = "1" register "TcssAuxOri" = "0" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + # Enable S0ix register "s0ix_enable" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index c381d2ef7d..417f23f83f 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -109,6 +109,9 @@ chip soc/intel/tigerlake register "TcssXhciEn" = "1" register "TcssAuxOri" = "0" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + # Enable S0ix register "s0ix_enable" = "1" |