diff options
| -rw-r--r-- | src/mainboard/amd/onyx/devicetree.cb | 13 | ||||
| -rw-r--r-- | src/soc/amd/genoa/Kconfig | 3 | ||||
| -rw-r--r-- | src/soc/amd/genoa/early_fch.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/genoa/include/soc/acpi.h | 8 | ||||
| -rw-r--r-- | src/soc/amd/genoa/include/soc/lpc.h | 16 | ||||
| -rw-r--r-- | src/soc/amd/genoa/include/soc/pci_devs.h | 48 |
6 files changed, 90 insertions, 0 deletions
diff --git a/src/mainboard/amd/onyx/devicetree.cb b/src/mainboard/amd/onyx/devicetree.cb index 5f447b2540..2b37b761fd 100644 --- a/src/mainboard/amd/onyx/devicetree.cb +++ b/src/mainboard/amd/onyx/devicetree.cb @@ -1,5 +1,18 @@ chip soc/amd/genoa + # eSPI configuration + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN, + .io_mode = ESPI_IO_MODE_SINGLE, + .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, + .crc_check_enable = 1, + .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, + .periph_ch_en = 0, + .vw_ch_en = 0, + .oob_ch_en = 0, + .flash_ch_en = 0, + }" + device domain 0 on end diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig index d3803652c7..3044d717aa 100644 --- a/src/soc/amd/genoa/Kconfig +++ b/src/soc/amd/genoa/Kconfig @@ -12,9 +12,12 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H + select SOC_AMD_COMMON_BLOCK_HAS_ESPI + select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_TSC + select SOC_AMD_COMMON_BLOCK_USE_ESPI select X86_CUSTOM_BOOTMEDIA config USE_EXP_X86_64_SUPPORT diff --git a/src/soc/amd/genoa/early_fch.c b/src/soc/amd/genoa/early_fch.c index 21e988e763..8de43e22e3 100644 --- a/src/soc/amd/genoa/early_fch.c +++ b/src/soc/amd/genoa/early_fch.c @@ -14,6 +14,8 @@ void fch_pre_init(void) fch_enable_cf9_io(); enable_aoac_devices(); + + configure_espi_with_mb_hook(); } /* After console init */ diff --git a/src/soc/amd/genoa/include/soc/acpi.h b/src/soc/amd/genoa/include/soc/acpi.h new file mode 100644 index 0000000000..51fa91ef93 --- /dev/null +++ b/src/soc/amd/genoa/include/soc/acpi.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef AMD_GENOA_ACPI_H +#define AMD_GENOA_ACPI_H + +#define ACPI_SCI_IRQ 9 + +#endif /* AMD_GENOA_ACPI_H */ diff --git a/src/soc/amd/genoa/include/soc/lpc.h b/src/soc/amd/genoa/include/soc/lpc.h new file mode 100644 index 0000000000..f98ffe8ef8 --- /dev/null +++ b/src/soc/amd/genoa/include/soc/lpc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_GENOA_LPC_H +#define AMD_GENOA_LPC_H + +#define SPI_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_ALIGNMENT BIT(8) +#define SPI_BASE_RESERVED (BIT(5) | BIT(6) | BIT(7)) +#define PSP_SPI_MMIO_SEL BIT(4) +#define ROUTE_TPM_2_SPI BIT(3) +#define SPI_ABORT_ENABLE BIT(2) +#define SPI_ROM_ENABLE BIT(1) +#define SPI_ROM_ALT_ENABLE BIT(0) +#define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4)) + +#endif /* AMD_GENOA_LPC_H */ diff --git a/src/soc/amd/genoa/include/soc/pci_devs.h b/src/soc/amd/genoa/include/soc/pci_devs.h new file mode 100644 index 0000000000..d314deb4a5 --- /dev/null +++ b/src/soc/amd/genoa/include/soc/pci_devs.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_GENOA_PCI_DEVS_H +#define AMD_GENOA_PCI_DEVS_H + +#include <device/pci_def.h> +#include <amdblocks/pci_devs.h> + +/* GNB Root Complex */ +#define GNB_DEV 0x0 +#define GNB_FUNC 0 +#define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC) +#define SOC_GNB_DEV _SOC_DEV(GNB_DEV, GNB_FUNC) + +/* SMBUS */ +#define SMBUS_DEV 0x14 +#define SMBUS_FUNC 0 +#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) +#define SOC_SMBUS_DEV _SOC_DEV(SMBUS_DEV, SMBUS_FUNC) + +/* Data Fabric functions */ +#define DF_DEV 0x18 + +#define DF_F0_DEVFN PCI_DEVFN(DF_DEV, 0) +#define SOC_DF_F0_DEV _SOC_DEV(DF_DEV, 0) + +#define DF_F1_DEVFN PCI_DEVFN(DF_DEV, 1) +#define SOC_DF_F1_DEV _SOC_DEV(DF_DEV, 1) + +#define DF_F2_DEVFN PCI_DEVFN(DF_DEV, 2) +#define SOC_DF_F2_DEV _SOC_DEV(DF_DEV, 2) + +#define DF_F3_DEVFN PCI_DEVFN(DF_DEV, 3) +#define SOC_DF_F3_DEV _SOC_DEV(DF_DEV, 3) + +#define DF_F4_DEVFN PCI_DEVFN(DF_DEV, 4) +#define SOC_DF_F4_DEV _SOC_DEV(DF_DEV, 4) + +#define DF_F5_DEVFN PCI_DEVFN(DF_DEV, 5) +#define SOC_DF_F5_DEV _SOC_DEV(DF_DEV, 5) + +#define DF_F6_DEVFN PCI_DEVFN(DF_DEV, 6) +#define SOC_DF_F6_DEV _SOC_DEV(DF_DEV, 6) + +#define DF_F7_DEVFN PCI_DEVFN(DF_DEV, 7) +#define SOC_DF_F7_DEV _SOC_DEV(DF_DEV, 7) + +#endif |