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-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h22
1 files changed, 12 insertions, 10 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
index 3c6f9a7408..f36b56806d 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
@@ -56,6 +56,18 @@ are permitted provided that the following conditions are met:
#define MAX_LOGIC_IIO_STACK (MAX_IIO_STACK+2)
+// RC version number structure.
+typedef struct {
+ uint8_t Major;
+ uint8_t Minor;
+ uint8_t Revision;
+ uint16_t BuildNumber;
+} RC_VERSION;
+// Note: the struct is not packed for a reason: it is not packed in FSP code.
+// It is a bug acknowledged by Intel (IPS case 00600003) that has been fixed for SRP
+// but won't be fixed for CPX.
+_Static_assert(sizeof(RC_VERSION) == 6, "Incorrect size of struct 'RC_VERSION'");
+
#pragma pack(1)
//--------------------------------------------------------------------------------------//
@@ -77,16 +89,6 @@ typedef enum {
TYPE_MAX_MMIO_BAR
} MMIO_BARS;
-///
-/// RC version number structure.
-///
-typedef struct {
- uint8_t Major;
- uint8_t Minor;
- uint8_t Revision;
- uint16_t BuildNumber;
-} RC_VERSION;
-
/**
IIO PCIe Ports
**/