diff options
45 files changed, 90 insertions, 46 deletions
diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 033af6ec21..7221f955f6 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <chip.h> #include <bootstate.h> #include <console/console.h> #include <cpu/amd/mtrr.h> @@ -30,6 +29,8 @@ #include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper_call.h> +#include "chip.h" + /* Supplied by i2c.c */ extern struct device_operations stoneyridge_i2c_mmio_ops; extern const char *i2c_acpi_name(const struct device *dev); diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 9380d1f945..42963c0941 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -13,13 +13,11 @@ * GNU General Public License for more details. */ - #include <device/pci_ops.h> #include <arch/ioapic.h> #include <arch/acpi.h> #include <arch/acpigen.h> #include <cbmem.h> -#include <chip.h> #include <console/console.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/lapic_def.h> @@ -42,6 +40,8 @@ #include <string.h> #include <arch/bert_storage.h> +#include "chip.h" + static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 92922c0662..12ee2a8aca 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -24,7 +24,6 @@ #include <commonlib/helpers.h> #include <console/console.h> #include <device/device.h> -#include <chip.h> #include <program_loading.h> #include <romstage_handoff.h> #include <elog.h> @@ -35,6 +34,8 @@ #include <soc/southbridge.h> #include <amdblocks/psp.h> +#include "chip.h" + void __weak mainboard_romstage_entry(int s3_resume) { /* By default, don't do anything */ diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index 7617d53644..4be13cdea3 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <chip.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -23,6 +22,8 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> +#include "chip.h" + static void pci_domain_set_resources(struct device *dev) { printk(BIOS_SPEW, "%s/%s (%s)\n", diff --git a/src/soc/intel/braswell/include/soc/ramstage.h b/src/soc/intel/braswell/include/soc/ramstage.h index d735de5885..f197bc8e1f 100644 --- a/src/soc/intel/braswell/include/soc/ramstage.h +++ b/src/soc/intel/braswell/include/soc/ramstage.h @@ -17,10 +17,11 @@ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ -#include <chip.h> #include <device/device.h> #include <fsp/ramstage.h> +#include "../../chip.h" + #define V_PCH_LPC_RID_A0 0x00 // A0 Stepping #define V_PCH_LPC_RID_A1 0x04 // A1 Stepping #define V_PCH_LPC_RID_A2 0x08 // A2 Stepping diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index ae2eac8e20..342b05cf50 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -22,7 +22,6 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <arch/cbfs.h> -#include <chip.h> #include <cpu/x86/mtrr.h> #include <console/console.h> #include <device/device.h> @@ -44,6 +43,8 @@ #include <build.h> #include <pc80/mc146818rtc.h> +#include "../chip.h" + void program_base_addresses(void) { uint32_t reg; diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 19469dc94f..209e7c52d4 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -19,7 +19,6 @@ #include <arch/acpigen.h> #include <arch/smp/mpspec.h> #include <cbmem.h> -#include <chip.h> #include <console/console.h> #include <device/mmio.h> #include <device/pci_ops.h> @@ -38,6 +37,8 @@ #include <vendorcode/google/chromeos/gnvs.h> #include <wrdd.h> +#include "chip.h" + /* * List of supported C-states in this processor. */ diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 845e9ef34f..1bd34c34e0 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <chip.h> #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> @@ -27,6 +26,8 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> +#include "chip.h" + #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 34b7891ea8..8552424749 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -16,7 +16,6 @@ #include <arch/cpu.h> #include <console/console.h> #include <device/pci.h> -#include <chip.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> @@ -35,6 +34,8 @@ #include <cpu/intel/microcode.h> #include <cpu/intel/common/common.h> +#include "chip.h" + /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { [0] = 0x00, diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index e334555ac0..4dfd15bc4a 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -17,7 +17,6 @@ #include <arch/io.h> #include <device/mmio.h> #include <bootstate.h> -#include <chip.h> #include <console/console.h> #include <console/post_codes.h> #include <cpu/x86/smm.h> @@ -35,6 +34,8 @@ #include <soc/systemagent.h> #include <stdlib.h> +#include "chip.h" + #define CAMERA1_CLK 0x8000 /* Camera 1 Clock */ #define CAMERA2_CLK 0x8080 /* Camera 2 Clock */ #define CAM_CLK_EN (1 << 1) diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 2b83275df1..61d2520693 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <chip.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -25,6 +24,8 @@ #include <soc/ramstage.h> #include <string.h> +#include "chip.h" + static const int serial_io_dev[] = { PCH_DEVFN_I2C0, PCH_DEVFN_I2C1, diff --git a/src/soc/intel/cannonlake/include/soc/ramstage.h b/src/soc/intel/cannonlake/include/soc/ramstage.h index 4a96185e6b..486839852c 100644 --- a/src/soc/intel/cannonlake/include/soc/ramstage.h +++ b/src/soc/intel/cannonlake/include/soc/ramstage.h @@ -17,11 +17,12 @@ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ -#include <chip.h> #include <device/device.h> #include <fsp/api.h> #include <fsp/util.h> +#include "../../chip.h" + void mainboard_silicon_init_params(FSP_S_CONFIG *params); void soc_init_pre_device(void *chip_info); diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index b2dd26dcf0..3512e2c4b4 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -16,7 +16,6 @@ #include <arch/ebda.h> #include <cbmem.h> -#include <chip.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -28,6 +27,8 @@ #include <soc/systemagent.h> #include <stdlib.h> +#include "chip.h" + void smm_region(void **start, size_t *size) { *start = (void *)sa_get_tseg_base(); diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index 5cd31f9f97..6834aa2d17 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -16,7 +16,6 @@ */ #include <bootstate.h> -#include <chip.h> #include <console/console.h> #include <device/mmio.h> #include <device/device.h> @@ -27,6 +26,8 @@ #include <soc/pci_devs.h> #include <soc/pm.h> +#include "chip.h" + /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index ce5863855e..c71e4b551a 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -14,7 +14,6 @@ */ #include <assert.h> -#include <chip.h> #include <cpu/x86/msr.h> #include <console/console.h> #include <fsp/util.h> @@ -25,6 +24,8 @@ #include <soc/romstage.h> #include <vendorcode/google/chromeos/chromeos.h> +#include "../chip.h" + static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) { unsigned int i; diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index c168da9a38..661c98a466 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <chip.h> #include <cpu/x86/mtrr.h> #include <cbmem.h> #include <console/console.h> @@ -30,6 +29,8 @@ #include <string.h> #include <timestamp.h> +#include "../chip.h" + #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 643fad645f..9af291700b 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include <chip.h> #include <console/console.h> #include <device/pci_def.h> #include <intelblocks/fast_spi.h> @@ -27,6 +26,8 @@ #include <soc/pcr_ids.h> #include <soc/pm.h> +#include "chip.h" + #define CSME0_FBE 0xf #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c index b1ea0935a7..fef7773cf9 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi.c +++ b/src/soc/intel/fsp_broadwell_de/acpi.c @@ -38,9 +38,10 @@ #include <soc/pattrs.h> #include <soc/pci_devs.h> #include <soc/broadwell_de.h> -#include <chip.h> #include <version.h> +#include "chip.h" + uint16_t get_pmbase(void) { return ACPI_BASE_ADDRESS; diff --git a/src/soc/intel/fsp_broadwell_de/chip.c b/src/soc/intel/fsp_broadwell_de/chip.c index ba825f4aae..a0b3f7ca6c 100644 --- a/src/soc/intel/fsp_broadwell_de/chip.c +++ b/src/soc/intel/fsp_broadwell_de/chip.c @@ -22,7 +22,8 @@ #include <drivers/intel/fsp1_0/fsp_util.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> -#include <chip.h> + +#include "chip.h" static void pci_domain_set_resources(struct device *dev) { diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c index fd8ca38ab6..edb313e7d5 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c @@ -25,9 +25,10 @@ #include <drivers/intel/fsp1_0/fsp_util.h> #include <soc/pci_devs.h> #include <soc/romstage.h> -#include <chip.h> #include <fsp.h> +#include "../chip.h" + /* Copy the default UPD region and settings to a buffer for modification */ static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) { diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c index a1e183adca..2f87cad9da 100644 --- a/src/soc/intel/fsp_broadwell_de/southcluster.c +++ b/src/soc/intel/fsp_broadwell_de/southcluster.c @@ -32,7 +32,8 @@ #include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> -#include <chip.h> + +#include "chip.h" typedef struct soc_intel_fsp_broadwell_de_config config_t; diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 1ad89600c1..f16469eb63 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -18,7 +18,6 @@ #include <device/mmio.h> #include <arch/smp/mpspec.h> #include <cbmem.h> -#include <chip.h> #include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/pmclib.h> @@ -32,6 +31,8 @@ #include <vendorcode/google/chromeos/gnvs.h> #include <wrdd.h> +#include "chip.h" + /* * List of supported C-states in this processor. */ diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 464c25e509..11d14de084 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <chip.h> #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> @@ -28,6 +27,8 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> +#include "chip.h" + #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 62bcff6844..b1776a09a4 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -16,7 +16,6 @@ #include <arch/cpu.h> #include <console/console.h> #include <device/pci.h> -#include <chip.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> @@ -33,6 +32,8 @@ #include <soc/pm.h> #include <soc/smm.h> +#include "chip.h" + static void soc_fsp_load(void) { fsps_load(romstage_handoff_is_resume()); diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index 3ada73d79c..c1e6dd0d4a 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -16,7 +16,6 @@ #include <arch/io.h> #include <device/mmio.h> #include <bootstate.h> -#include <chip.h> #include <console/console.h> #include <console/post_codes.h> #include <cpu/x86/smm.h> @@ -34,6 +33,8 @@ #include <soc/systemagent.h> #include <stdlib.h> +#include "chip.h" + #define CAMERA1_CLK 0x8000 /* Camera 1 Clock */ #define CAMERA2_CLK 0x8080 /* Camera 2 Clock */ #define CAM_CLK_EN (1 << 1) diff --git a/src/soc/intel/icelake/include/soc/ramstage.h b/src/soc/intel/icelake/include/soc/ramstage.h index d0b500d135..d78380a6dc 100644 --- a/src/soc/intel/icelake/include/soc/ramstage.h +++ b/src/soc/intel/icelake/include/soc/ramstage.h @@ -16,11 +16,12 @@ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ -#include <chip.h> #include <device/device.h> #include <fsp/api.h> #include <fsp/util.h> +#include "../../chip.h" + void mainboard_silicon_init_params(FSP_S_CONFIG *params); void soc_init_pre_device(void *chip_info); diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 821162e768..7d6e4e6592 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -15,7 +15,6 @@ #include <arch/ebda.h> #include <cbmem.h> -#include <chip.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -27,6 +26,8 @@ #include <soc/systemagent.h> #include <stdlib.h> +#include "chip.h" + void smm_region(void **start, size_t *size) { *start = (void *)sa_get_tseg_base(); diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c index ac48da24f8..8f61d70955 100644 --- a/src/soc/intel/icelake/pmc.c +++ b/src/soc/intel/icelake/pmc.c @@ -14,7 +14,6 @@ */ #include <bootstate.h> -#include <chip.h> #include <console/console.h> #include <device/mmio.h> #include <device/device.h> @@ -25,6 +24,8 @@ #include <soc/pci_devs.h> #include <soc/pm.h> +#include "chip.h" + /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index b0a2b6c0cd..1a0c4ffaee 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <chip.h> #include <cpu/x86/mtrr.h> #include <cbmem.h> #include <console/console.h> @@ -30,6 +29,8 @@ #include <string.h> #include <timestamp.h> +#include "../chip.h" + #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index ddf642003f..5c00b63720 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <chip.h> #include <console/console.h> #include <device/pci_def.h> #include <intelblocks/fast_spi.h> @@ -25,6 +24,8 @@ #include <soc/pcr_ids.h> #include <soc/pm.h> +#include "chip.h" + #define CSME0_FBE 0xf #define CSME0_BAR 0x0 #define CSME0_FID 0xb0 diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h index 67e37de943..56be795dcd 100644 --- a/src/soc/intel/quark/include/soc/ramstage.h +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -18,11 +18,12 @@ #define _SOC_RAMSTAGE_H_ #include <arch/cpu.h> -#include <chip.h> #include <device/device.h> #include <device/pci_ops.h> #include <soc/QuarkNcSocId.h> +#include "../../chip.h" + void mainboard_gpio_i2c_init(struct device *dev); asmlinkage void chipset_teardown_car(void); diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 26a131ddc2..bd944dac16 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -21,7 +21,6 @@ #include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <cbmem.h> -#include <chip.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <cpu/x86/msr.h> @@ -51,6 +50,8 @@ #include <wrdd.h> #include <device/pci_ops.h> +#include "chip.h" + /* * List of suported C-states in this processor. */ diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 0f6c8a85d4..c95a8d80e8 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ #include <device/pci_ops.h> -#include <chip.h> #include <device/device.h> #include <device/pci_def.h> #include <intelblocks/cse.h> @@ -37,6 +36,8 @@ #include <soc/pmc.h> #include <soc/smbus.h> +#include "../chip.h" + #define PCR_DMI_DMICTL 0x2234 #define PCR_DMI_DMICTL_SRLOCK (1 << 31) #define PCR_DMI_ACPIBA 0x27B4 diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 9094348e78..6f90178f52 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -15,7 +15,6 @@ */ #include <arch/acpi.h> -#include <chip.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -33,6 +32,8 @@ #include <soc/ramstage.h> #include <string.h> +#include "chip.h" + void soc_init_pre_device(void *chip_info) { /* Snapshot the current GPIO IRQ polarities. FSP is setting a diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index c16a913218..d179598699 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <chip.h> #include <bootmode.h> #include <bootstate.h> #include <device/pci.h> @@ -42,6 +41,8 @@ #include <soc/systemagent.h> #include <string.h> +#include "chip.h" + struct pcie_entry { unsigned int devfn; unsigned int func_count; diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 47d484162d..52b0e194e6 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <chip.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> @@ -46,6 +45,8 @@ #include <soc/systemagent.h> #include <timer.h> +#include "chip.h" + /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { [0] = 0x00, diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index c69dffbe41..5d7e1e0034 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -18,7 +18,6 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <bootstate.h> -#include <chip.h> #include <console/console.h> #include <console/post_codes.h> #include <cpu/x86/mp.h> @@ -41,6 +40,8 @@ #include <stdlib.h> #include <timer.h> +#include "chip.h" + #define PSF_BASE_ADDRESS 0xA00 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) diff --git a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h index 3ab0efa7e5..2071d58b49 100644 --- a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h +++ b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h @@ -17,11 +17,12 @@ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ -#include <chip.h> #include <device/device.h> #include <fsp/ramstage.h> #include <fsp/soc_binding.h> +#include "../../../chip.h" + #define FSP_SIL_UPD SILICON_INIT_UPD #define FSP_MEM_UPD MEMORY_INIT_UPD diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h index e75b350049..e5660a6f66 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h @@ -17,11 +17,12 @@ #ifndef _SOC_RAMSTAGE_H_ #define _SOC_RAMSTAGE_H_ -#include <chip.h> #include <device/device.h> #include <fsp/api.h> #include <fsp/util.h> +#include "../../../chip.h" + #define FSP_SIL_UPD FSP_S_CONFIG #define FSP_MEM_UPD FSP_M_CONFIG diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 60a7070408..fde916a922 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -17,7 +17,6 @@ #include <arch/ebda.h> #include <device/mmio.h> #include <cbmem.h> -#include <chip.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -29,6 +28,8 @@ #include <soc/systemagent.h> #include <stdlib.h> +#include "chip.h" + size_t mmap_region_granularity(void) { if (CONFIG(HAVE_SMI_HANDLER)) diff --git a/src/soc/intel/skylake/pei_data.c b/src/soc/intel/skylake/pei_data.c index a2887ac4c4..203a1d8e36 100644 --- a/src/soc/intel/skylake/pei_data.c +++ b/src/soc/intel/skylake/pei_data.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <chip.h> #include <console/streams.h> #include <device/device.h> #include <device/pci_def.h> @@ -25,6 +24,8 @@ #include <soc/pei_data.h> #include <soc/pei_wrapper.h> +#include "chip.h" + static void ABI_X86 send_to_console(unsigned char b) { console_tx_byte(b); diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index 5ff05c26c2..01def44b06 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -16,7 +16,6 @@ */ #include <bootstate.h> -#include <chip.h> #include <console/console.h> #include <device/mmio.h> #include <device/device.h> @@ -28,6 +27,8 @@ #include <soc/pci_devs.h> #include <soc/pm.h> +#include "chip.h" + void pmc_set_disb(void) { /* Set the DISB after DRAM init */ diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index d8188f6924..0501b04493 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -17,7 +17,6 @@ #include <arch/cbfs.h> #include <arch/early_variables.h> #include <assert.h> -#include <chip.h> #include <console/console.h> #include <cpu/x86/mtrr.h> #include <device/device.h> @@ -37,6 +36,8 @@ #include <stdint.h> #include <vendorcode/google/chromeos/chromeos.h> +#include "../chip.h" + /* SOC initialization before RAM is enabled */ void soc_pre_ram_init(struct romstage_params *params) { diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index dcfc3632ca..1e81d7aa05 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -20,7 +20,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cbmem.h> -#include <chip.h> #include <console/console.h> #include <device/pci_def.h> #include <fsp/util.h> @@ -37,6 +36,8 @@ #include <timestamp.h> #include <security/vboot/vboot_common.h> +#include "../chip.h" + #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ diff --git a/src/soc/intel/skylake/thermal.c b/src/soc/intel/skylake/thermal.c index 711b714b04..97cd1b7779 100644 --- a/src/soc/intel/skylake/thermal.c +++ b/src/soc/intel/skylake/thermal.c @@ -15,7 +15,6 @@ #include <device/mmio.h> #include <device/pci_ops.h> -#include <chip.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -23,6 +22,8 @@ #include <soc/pci_devs.h> #include <soc/thermal.h> +#include "chip.h" + #define MAX_TRIP_TEMP 205 #define DEFAULT_TRIP_TEMP 50 |