diff options
| -rw-r--r-- | src/device/pciexp_device.c | 8 | ||||
| -rw-r--r-- | src/include/device/pci_def.h | 10 |
2 files changed, 8 insertions, 10 deletions
diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 3153e0eb37..0b7c649d93 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -140,9 +140,9 @@ static bool pciexp_is_ltr_supported(struct device *dev, unsigned int cap) { unsigned int val; - val = pci_read_config16(dev, cap + PCI_EXP_DEV_CAP2_OFFSET); + val = pci_read_config16(dev, cap + PCI_EXP_DEVCAP2); - if (val & LTR_MECHANISM_SUPPORT) + if (val & PCI_EXP_DEVCAP2_LTR) return true; return false; @@ -164,10 +164,10 @@ static void pciexp_configure_ltr(struct device *dev) return; } - cap += PCI_EXP_DEV_CTL_STS2_CAP_OFFSET; + cap += PCI_EXP_DEVCTL2; /* Enable LTR for device */ - pci_update_config32(dev, cap, ~LTR_MECHANISM_EN, LTR_MECHANISM_EN); + pci_update_config32(dev, cap, ~PCI_EXP_DEV2_LTR, PCI_EXP_DEV2_LTR); /* Configure Max Snoop Latency */ pciexp_config_max_latency(dev->bus->dev, dev); diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index e0d891eeb9..b0558fa67e 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -386,12 +386,6 @@ #define PCI_EXP_DEVCAP 4 /* Device capabilities */ #define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */ #define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */ -#define PCI_EXP_DEV_CAP2_OFFSET 0x24 /* Device Capabilities 2 offset */ -/* LTR mechanism supported.Bit 11 of Device Cap 2 Register */ -#define LTR_MECHANISM_SUPPORT (1 << 11) -#define PCI_EXP_DEV_CTL_STS2_CAP_OFFSET 0x28 /* Device Control 2 offset */ -/* LTR mechanism enable. Bit 10 of Device Control 2 Register */ -#define LTR_MECHANISM_EN (1 << 10) #define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */ #define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */ #define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */ @@ -445,6 +439,10 @@ #define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */ #define PCI_EXP_RTCAP 30 /* Root Capabilities */ #define PCI_EXP_RTSTA 32 /* Root Status */ +#define PCI_EXP_DEVCAP2 36 /* Device capabilities 2 */ +#define PCI_EXP_DEVCAP2_LTR 0x0800 /* LTR supported */ +#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ +#define PCI_EXP_DEV2_LTR 0x0400 /* LTR enabled */ /* Extended Capabilities (PCI-X 2.0 and Express) */ #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) |