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-rw-r--r--src/soc/mediatek/mt8188/Kconfig6
-rw-r--r--src/soc/mediatek/mt8188/Makefile.inc2
-rw-r--r--src/soc/mediatek/mt8188/include/soc/spm.h63
-rw-r--r--src/soc/mediatek/mt8188/soc.c8
-rw-r--r--src/soc/mediatek/mt8188/spm.c566
5 files changed, 628 insertions, 17 deletions
diff --git a/src/soc/mediatek/mt8188/Kconfig b/src/soc/mediatek/mt8188/Kconfig
index e42f6a38e8..972170edb2 100644
--- a/src/soc/mediatek/mt8188/Kconfig
+++ b/src/soc/mediatek/mt8188/Kconfig
@@ -39,6 +39,12 @@ config MCUPM_FIRMWARE
help
The file name of the MediaTek MCUPM firmware.
+config SPM_FIRMWARE
+ string
+ default "spm_firmware.bin"
+ help
+ The file name of the MediaTek SPM firmware.
+
config SSPM_FIRMWARE
string
default "sspm.bin"
diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc
index 98a96cdd64..70ec42ae7f 100644
--- a/src/soc/mediatek/mt8188/Makefile.inc
+++ b/src/soc/mediatek/mt8188/Makefile.inc
@@ -42,6 +42,7 @@ ramstage-y += ../common/mt6359p.c mt6359p.c
ramstage-y += ../common/pmif.c ../common/pmif_clk.c pmif_clk.c
ramstage-y += ../common/pmif_spi.c pmif_spi.c
ramstage-y += soc.c
+ramstage-y += ../common/spm.c spm.c
ramstage-y += ../common/sspm.c
ramstage-y += ../common/usb.c usb.c
@@ -54,6 +55,7 @@ mcu-firmware-files := \
$(CONFIG_DPM_DM_FIRMWARE) \
$(CONFIG_DPM_PM_FIRMWARE) \
$(CONFIG_MCUPM_FIRMWARE) \
+ $(CONFIG_SPM_FIRMWARE) \
$(CONFIG_SSPM_FIRMWARE)
$(foreach fw, $(call strip_quotes,$(mcu-firmware-files)), \
diff --git a/src/soc/mediatek/mt8188/include/soc/spm.h b/src/soc/mediatek/mt8188/include/soc/spm.h
index 8257d55555..734a810b1f 100644
--- a/src/soc/mediatek/mt8188/include/soc/spm.h
+++ b/src/soc/mediatek/mt8188/include/soc/spm.h
@@ -6,6 +6,7 @@
#include <device/mmio.h>
#include <soc/addressmap.h>
#include <soc/mtcmos.h>
+#include <soc/spm_common.h>
#include <types.h>
/* SPM READ/WRITE CFG */
@@ -37,7 +38,7 @@ DEFINE_BIT(REG_SYSCLK1_SRC_MD2_SRCCLKENA, 28)
#define SPM_WAKEUP_EVENT_MASK_CSYSPWREQ_B BIT(11)
/* DDR_EN_DBC_CON1 (0x10006000+0x0EC) */
-#define REG_ALL_DDR_EN_DBC_EN_LSB BIT(0)
+#define REG_ALL_DDR_EN_DBC_EN_LSB BIT(16)
/* SPM_DVFS_MISC (0x10006000+0x4AC) */
DEFINE_BIT(SPM_DVFS_FORCE_ENABLE_LSB, 2)
@@ -83,7 +84,20 @@ DEFINE_BIT(MD32PCM_CFGREG_SW_RSTN_RESET, 0)
DEFINE_BIT(ISRM_TWAM_BF, 2)
DEFINE_BITFIELD(ISRM_RET_IRQ_AUX_BF, 17, 8)
#define ISRM_TWAM BIT(2)
-#define ISRM_RET_IRQ_AUX (0x3ff << 8)
+#define ISRM_RET_IRQ1 BIT(9)
+#define ISRM_RET_IRQ2 BIT(10)
+#define ISRM_RET_IRQ3 BIT(11)
+#define ISRM_RET_IRQ4 BIT(12)
+#define ISRM_RET_IRQ5 BIT(13)
+#define ISRM_RET_IRQ6 BIT(14)
+#define ISRM_RET_IRQ7 BIT(15)
+#define ISRM_RET_IRQ8 BIT(16)
+#define ISRM_RET_IRQ9 BIT(17)
+#define ISRM_RET_IRQ_AUX ((ISRM_RET_IRQ9) | (ISRM_RET_IRQ8) | \
+ (ISRM_RET_IRQ7) | (ISRM_RET_IRQ6) | \
+ (ISRM_RET_IRQ5) | (ISRM_RET_IRQ4) | \
+ (ISRM_RET_IRQ3) | (ISRM_RET_IRQ2) | \
+ (ISRM_RET_IRQ1))
#define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX)
#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM)
@@ -104,6 +118,14 @@ DEFINE_BITFIELD(ISRM_RET_IRQ_AUX_BF, 17, 8)
/* SPM_SWINT */
#define PCM_SW_INT_ALL 0x3ff
+#define SPM_ACK_CHK_3_SEL_HW_S1 0x00350098
+#define SPM_ACK_CHK_3_HW_S1_CNT 1
+
+DEFINE_BIT(SPM_ACK_CHK_3_CON_CLR_ALL, 1)
+DEFINE_BIT(SPM_ACK_CHK_3_CON_EN_0, 4)
+DEFINE_BIT(SPM_ACK_CHK_3_CON_EN_1, 8)
+DEFINE_BIT(SPM_ACK_CHK_3_CON_HW_MODE_TRIG, 11)
+
struct pwr_ctrl {
/* for SPM */
uint32_t pcm_flags;
@@ -235,6 +257,10 @@ struct pwr_ctrl {
uint8_t reg_bak_psri_vrf18_req_mask_b;
/* [29] */
uint8_t reg_bak_psri_ddr_en_mask_b;
+ /* [30] */
+ uint8_t reg_cam_ddren_req_mask_b;
+ /* [31] */
+ uint8_t reg_img_ddren_req_mask_b;
/* SPM_SRC2_MASK */
/* [0] */
@@ -896,7 +922,19 @@ struct mtk_spm_regs {
u32 spm_twam_window_len;
u32 spm_twam_idle_sel;
u32 spm_twam_event_clear;
- u8 reserved32[1376];
+ u8 reserved_69a0[96];
+ u32 md32pcm_cfgreg_sw_rstn;
+ u8 reserved_6a04[508];
+ u32 md32pcm_dma0_src;
+ u32 md32pcm_dma0_dst;
+ u32 md32pcm_dma0_wppt;
+ u32 md32pcm_dma0_wpto;
+ u32 md32pcm_dma0_count;
+ u32 md32pcm_dma0_con;
+ u32 md32pcm_dma0_start;
+ u8 reserved_6c1c[8];
+ u32 md32pcm_dma0_rlct;
+ u8 reserved32[728];
u32 pmsr_last_dat;
u32 pmsr_last_cnt;
u32 pmsr_last_ack;
@@ -938,21 +976,14 @@ check_member(mtk_spm_regs, audio_pwr_con, 0x034c);
check_member(mtk_spm_regs, adsp_pwr_con, 0x0354);
check_member(mtk_spm_regs, ap_mdsrc_req, 0x043c);
check_member(mtk_spm_regs, ulposc_con, 0x644);
+check_member(mtk_spm_regs, md32pcm_cfgreg_sw_rstn, 0xa00);
+check_member(mtk_spm_regs, md32pcm_dma0_src, 0xc00);
+check_member(mtk_spm_regs, md32pcm_dma0_rlct, 0xc24);
+check_member(mtk_spm_regs, pmsr_last_dat, 0xf00);
+check_member(mtk_spm_regs, spm_pmsr_len_con2, 0xff4);
static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE;
-struct pcm_desc {
- u32 pmem_words;
- u32 total_words;
- u32 pmem_start;
- u32 dmem_start;
-};
-
-struct dyna_load_pcm {
- u8 *buf; /* binary array */
- struct pcm_desc desc;
-};
-
static const struct power_domain_data disp[] = {
{
.pwr_con = &mtk_spm->vppsys0_pwr_con,
@@ -1001,6 +1032,4 @@ static const struct power_domain_data audio[] = {
},
};
-int spm_init(void);
-
#endif /* SOC_MEDIATEK_MT8188_SPM_H */
diff --git a/src/soc/mediatek/mt8188/soc.c b/src/soc/mediatek/mt8188/soc.c
index e80fc0d9ab..bcbea03c89 100644
--- a/src/soc/mediatek/mt8188/soc.c
+++ b/src/soc/mediatek/mt8188/soc.c
@@ -9,6 +9,7 @@
#include <soc/emi.h>
#include <soc/mcupm.h>
#include <soc/mmu_operations.h>
+#include <soc/spm.h>
#include <soc/sspm.h>
#include <symbols.h>
@@ -33,6 +34,13 @@ static void soc_init(struct device *dev)
if (dpm_init())
printk(BIOS_ERR, "dpm init failed, DVFS may not work\n");
+ /*
+ * For MT8188, SPM will handshake with DPM to do initialization, so
+ * this must run after dpm_init().
+ */
+ if (spm_init())
+ printk(BIOS_ERR, "spm init failed, system suspend may not work\n");
+
if (CONFIG(MTK_DFD))
dfd_init();
}
diff --git a/src/soc/mediatek/mt8188/spm.c b/src/soc/mediatek/mt8188/spm.c
new file mode 100644
index 0000000000..fd4648fbba
--- /dev/null
+++ b/src/soc/mediatek/mt8188/spm.c
@@ -0,0 +1,566 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#include <assert.h>
+#include <soc/mcu_common.h>
+#include <soc/pll.h>
+#include <soc/spm.h>
+
+static struct pwr_ctrl spm_init_ctrl = {
+ /* For SPM, this flag is not auto-gen. */
+ .pcm_flags = SPM_FLAG_DISABLE_VCORE_DVS |
+ SPM_FLAG_DISABLE_VCORE_DFS |
+ SPM_FLAG_RUN_COMMON_SCENARIO,
+ /* SPM_AP_STANDBY_CON */
+ /* [0] */
+ .reg_wfi_op = 0,
+ /* [1] */
+ .reg_wfi_type = 0,
+ /* [2] */
+ .reg_mp0_cputop_idle_mask = 0,
+ /* [3] */
+ .reg_mp1_cputop_idle_mask = 0,
+ /* [4] */
+ .reg_mcusys_idle_mask = 0,
+ /* [25] */
+ .reg_md_apsrc_1_sel = 0,
+ /* [26] */
+ .reg_md_apsrc_0_sel = 0,
+ /* [29] */
+ .reg_conn_apsrc_sel = 0,
+
+ /* SPM_SRC_REQ */
+ /* [0] */
+ .reg_spm_apsrc_req = 0,
+ /* [1] */
+ .reg_spm_f26m_req = 0,
+ /* [3] */
+ .reg_spm_infra_req = 0,
+ /* [4] */
+ .reg_spm_vrf18_req = 0,
+ /* [7] */
+ .reg_spm_ddr_en_req = 0,
+ /* [8] */
+ .reg_spm_dvfs_req = 0,
+ /* [9] */
+ .reg_spm_sw_mailbox_req = 0,
+ /* [10] */
+ .reg_spm_sspm_mailbox_req = 0,
+ /* [11] */
+ .reg_spm_adsp_mailbox_req = 0,
+ /* [12] */
+ .reg_spm_scp_mailbox_req = 0,
+
+
+ /* SPM_SRC_MASK */
+ /* [0] */
+ .reg_sspm_srcclkena_0_mask_b = 1,
+ /* [1] */
+ .reg_sspm_infra_req_0_mask_b = 1,
+ /* [2] */
+ .reg_sspm_apsrc_req_0_mask_b = 1,
+ /* [3] */
+ .reg_sspm_vrf18_req_0_mask_b = 1,
+ /* [4] */
+ .reg_sspm_ddr_en_0_mask_b = 1,
+ /* [5] */
+ .reg_scp_srcclkena_mask_b = 1,
+ /* [6] */
+ .reg_scp_infra_req_mask_b = 1,
+ /* [7] */
+ .reg_scp_apsrc_req_mask_b = 1,
+ /* [8] */
+ .reg_scp_vrf18_req_mask_b = 1,
+ /* [9] */
+ .reg_scp_ddr_en_mask_b = 1,
+ /* [10] */
+ .reg_audio_dsp_srcclkena_mask_b = 1,
+ /* [11] */
+ .reg_audio_dsp_infra_req_mask_b = 1,
+ /* [12] */
+ .reg_audio_dsp_apsrc_req_mask_b = 1,
+ /* [13] */
+ .reg_audio_dsp_vrf18_req_mask_b = 1,
+ /* [14] */
+ .reg_audio_dsp_ddr_en_mask_b = 1,
+ /* [15] */
+ .reg_apu_srcclkena_mask_b = 1,
+ /* [16] */
+ .reg_apu_infra_req_mask_b = 1,
+ /* [17] */
+ .reg_apu_apsrc_req_mask_b = 1,
+ /* [18] */
+ .reg_apu_vrf18_req_mask_b = 1,
+ /* [19] */
+ .reg_apu_ddr_en_mask_b = 1,
+ /* [20] */
+ .reg_cpueb_srcclkena_mask_b = 1,
+ /* [21] */
+ .reg_cpueb_infra_req_mask_b = 1,
+ /* [22] */
+ .reg_cpueb_apsrc_req_mask_b = 1,
+ /* [23] */
+ .reg_cpueb_vrf18_req_mask_b = 1,
+ /* [24] */
+ .reg_cpueb_ddr_en_mask_b = 1,
+ /* [25] */
+ .reg_bak_psri_srcclkena_mask_b = 0,
+ /* [26] */
+ .reg_bak_psri_infra_req_mask_b = 0,
+ /* [27] */
+ .reg_bak_psri_apsrc_req_mask_b = 0,
+ /* [28] */
+ .reg_bak_psri_vrf18_req_mask_b = 0,
+ /* [29] */
+ .reg_bak_psri_ddr_en_mask_b = 0,
+ /* [30] */
+ .reg_cam_ddren_req_mask_b = 1,
+ /* [31] */
+ .reg_img_ddren_req_mask_b = 1,
+
+ /* SPM_SRC2_MASK */
+ /* [0] */
+ .reg_msdc0_srcclkena_mask_b = 1,
+ /* [1] */
+ .reg_msdc0_infra_req_mask_b = 1,
+ /* [2] */
+ .reg_msdc0_apsrc_req_mask_b = 1,
+ /* [3] */
+ .reg_msdc0_vrf18_req_mask_b = 1,
+ /* [4] */
+ .reg_msdc0_ddr_en_mask_b = 1,
+ /* [5] */
+ .reg_msdc1_srcclkena_mask_b = 1,
+ /* [6] */
+ .reg_msdc1_infra_req_mask_b = 1,
+ /* [7] */
+ .reg_msdc1_apsrc_req_mask_b = 1,
+ /* [8] */
+ .reg_msdc1_vrf18_req_mask_b = 1,
+ /* [9] */
+ .reg_msdc1_ddr_en_mask_b = 1,
+ /* [10] */
+ .reg_msdc2_srcclkena_mask_b = 1,
+ /* [11] */
+ .reg_msdc2_infra_req_mask_b = 1,
+ /* [12] */
+ .reg_msdc2_apsrc_req_mask_b = 1,
+ /* [13] */
+ .reg_msdc2_vrf18_req_mask_b = 1,
+ /* [14] */
+ .reg_msdc2_ddr_en_mask_b = 1,
+ /* [15] */
+ .reg_ufs_srcclkena_mask_b = 1,
+ /* [16] */
+ .reg_ufs_infra_req_mask_b = 1,
+ /* [17] */
+ .reg_ufs_apsrc_req_mask_b = 1,
+ /* [18] */
+ .reg_ufs_vrf18_req_mask_b = 1,
+ /* [19] */
+ .reg_ufs_ddr_en_mask_b = 1,
+ /* [20] */
+ .reg_usb_srcclkena_mask_b = 1,
+ /* [21] */
+ .reg_usb_infra_req_mask_b = 1,
+ /* [22] */
+ .reg_usb_apsrc_req_mask_b = 1,
+ /* [23] */
+ .reg_usb_vrf18_req_mask_b = 1,
+ /* [24] */
+ .reg_usb_ddr_en_mask_b = 1,
+ /* [25] */
+ .reg_pextp_p0_srcclkena_mask_b = 1,
+ /* [26] */
+ .reg_pextp_p0_infra_req_mask_b = 1,
+ /* [27] */
+ .reg_pextp_p0_apsrc_req_mask_b = 1,
+ /* [28] */
+ .reg_pextp_p0_vrf18_req_mask_b = 1,
+ /* [29] */
+ .reg_pextp_p0_ddr_en_mask_b = 1,
+
+ /* SPM_SRC3_MASK */
+ /* [0] */
+ .reg_pextp_p1_srcclkena_mask_b = 1,
+ /* [1] */
+ .reg_pextp_p1_infra_req_mask_b = 1,
+ /* [2] */
+ .reg_pextp_p1_apsrc_req_mask_b = 1,
+ /* [3] */
+ .reg_pextp_p1_vrf18_req_mask_b = 1,
+ /* [4] */
+ .reg_pextp_p1_ddr_en_mask_b = 1,
+ /* [5] */
+ .reg_gce0_infra_req_mask_b = 1,
+ /* [6] */
+ .reg_gce0_apsrc_req_mask_b = 1,
+ /* [7] */
+ .reg_gce0_vrf18_req_mask_b = 1,
+ /* [8] */
+ .reg_gce0_ddr_en_mask_b = 1,
+ /* [9] */
+ .reg_gce1_infra_req_mask_b = 1,
+ /* [10] */
+ .reg_gce1_apsrc_req_mask_b = 1,
+ /* [11] */
+ .reg_gce1_vrf18_req_mask_b = 1,
+ /* [12] */
+ .reg_gce1_ddr_en_mask_b = 1,
+ /* [13] */
+ .reg_spm_srcclkena_reserved_mask_b = 1,
+ /* [14] */
+ .reg_spm_infra_req_reserved_mask_b = 1,
+ /* [15] */
+ .reg_spm_apsrc_req_reserved_mask_b = 1,
+ /* [16] */
+ .reg_spm_vrf18_req_reserved_mask_b = 1,
+ /* [17] */
+ .reg_spm_ddr_en_reserved_mask_b = 1,
+ /* [18] */
+ .reg_disp0_apsrc_req_mask_b = 1,
+ /* [19] */
+ .reg_disp0_ddr_en_mask_b = 1,
+ /* [20] */
+ .reg_disp1_apsrc_req_mask_b = 1,
+ /* [21] */
+ .reg_disp1_ddr_en_mask_b = 1,
+ /* [22] */
+ .reg_disp2_apsrc_req_mask_b = 1,
+ /* [23] */
+ .reg_disp2_ddr_en_mask_b = 1,
+ /* [24] */
+ .reg_disp3_apsrc_req_mask_b = 1,
+ /* [25] */
+ .reg_disp3_ddr_en_mask_b = 1,
+ /* [26] */
+ .reg_infrasys_apsrc_req_mask_b = 0,
+ /* [27] */
+ .reg_infrasys_ddr_en_mask_b = 1,
+
+ /* [28] */
+ .reg_cg_check_srcclkena_mask_b = 1,
+ /* [29] */
+ .reg_cg_check_apsrc_req_mask_b = 1,
+ /* [30] */
+ .reg_cg_check_vrf18_req_mask_b = 1,
+ /* [31] */
+ .reg_cg_check_ddr_en_mask_b = 1,
+
+ /* SPM_SRC4_MASK */
+ /* [8:0] */
+ .reg_mcusys_merge_apsrc_req_mask_b = 0,
+ /* [17:9] */
+ .reg_mcusys_merge_ddr_en_mask_b = 0,
+ /* [19:18] */
+ .reg_dramc_md32_infra_req_mask_b = 3,
+ /* [21:20] */
+ .reg_dramc_md32_vrf18_req_mask_b = 3,
+ /* [23:22] */
+ .reg_dramc_md32_ddr_en_mask_b = 0,
+ /* [24] */
+ .reg_dvfsrc_event_trigger_mask_b = 1,
+
+ /* SPM_WAKEUP_EVENT_MASK2 */
+ /* [3:0] */
+ .reg_sc_sw2spm_wakeup_mask_b = 0,
+ /* [4] */
+ .reg_sc_adsp2spm_wakeup_mask_b = 0,
+ /* [8:5] */
+ .reg_sc_sspm2spm_wakeup_mask_b = 0,
+ /* [9] */
+ .reg_sc_scp2spm_wakeup_mask_b = 0,
+ /* [10] */
+ .reg_csyspwrup_ack_mask = 0,
+ /* [11] */
+ .reg_csyspwrup_req_mask = 1,
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ /* [31:0] */
+ .reg_wakeup_event_mask = 0xC1382213,
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ /* [31:0] */
+ .reg_ext_wakeup_event_mask = 0xFFFFFFFF,
+};
+
+static void spm_hw_s1_state_monitor_pause(void)
+{
+ SET32_BITFIELDS(&mtk_spm->spm_ack_chk_con_3,
+ SPM_ACK_CHK_3_CON_HW_MODE_TRIG, 1,
+ SPM_ACK_CHK_3_CON_CLR_ALL, 1,
+ SPM_ACK_CHK_3_CON_EN_0, 0,
+ SPM_ACK_CHK_3_CON_EN_1, 0);
+}
+
+void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
+{
+ /* SPM_AP_STANDBY_CON */
+ write32(&mtk_spm->spm_ap_standby_con,
+ ((pwrctrl->reg_wfi_op & 0x1) << 0) |
+ ((pwrctrl->reg_wfi_type & 0x1) << 1) |
+ ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
+ ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
+ ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
+ ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
+ ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
+ ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
+
+ /* SPM_SRC_REQ */
+ write32(&mtk_spm->spm_src_req,
+ ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
+ ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
+ ((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
+ ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
+ ((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) |
+ ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
+ ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
+ ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
+ ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
+ ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
+
+ /* SPM_SRC_MASK */
+ write32(&mtk_spm->spm_src_mask,
+ ((pwrctrl->reg_sspm_srcclkena_0_mask_b & 0x1) << 0) |
+ ((pwrctrl->reg_sspm_infra_req_0_mask_b & 0x1) << 1) |
+ ((pwrctrl->reg_sspm_apsrc_req_0_mask_b & 0x1) << 2) |
+ ((pwrctrl->reg_sspm_vrf18_req_0_mask_b & 0x1) << 3) |
+ ((pwrctrl->reg_sspm_ddr_en_0_mask_b & 0x1) << 4) |
+ ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 5) |
+ ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 6) |
+ ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 7) |
+ ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 8) |
+ ((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 9) |
+ ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 10) |
+ ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 11) |
+ ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 12) |
+ ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 13) |
+ ((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 14) |
+ ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 15) |
+ ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 16) |
+ ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 17) |
+ ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 18) |
+ ((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 19) |
+ ((pwrctrl->reg_cpueb_srcclkena_mask_b & 0x1) << 20) |
+ ((pwrctrl->reg_cpueb_infra_req_mask_b & 0x1) << 21) |
+ ((pwrctrl->reg_cpueb_apsrc_req_mask_b & 0x1) << 22) |
+ ((pwrctrl->reg_cpueb_vrf18_req_mask_b & 0x1) << 23) |
+ ((pwrctrl->reg_cpueb_ddr_en_mask_b & 0x1) << 24) |
+ ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 25) |
+ ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 26) |
+ ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 27) |
+ ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 28) |
+ ((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 29) |
+ ((pwrctrl->reg_cam_ddren_req_mask_b & 0x1) << 30) |
+ ((pwrctrl->reg_img_ddren_req_mask_b & 0x1) << 31));
+
+ /* SPM_SRC2_MASK */
+ write32(&mtk_spm->spm_src2_mask,
+ ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 0) |
+ ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 1) |
+ ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 2) |
+ ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 3) |
+ ((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 4) |
+ ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 5) |
+ ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 6) |
+ ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 7) |
+ ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 8) |
+ ((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 9) |
+ ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 10) |
+ ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 11) |
+ ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 12) |
+ ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 13) |
+ ((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 14) |
+ ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 15) |
+ ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 16) |
+ ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 17) |
+ ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 18) |
+ ((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 19) |
+ ((pwrctrl->reg_usb_srcclkena_mask_b & 0x1) << 20) |
+ ((pwrctrl->reg_usb_infra_req_mask_b & 0x1) << 21) |
+ ((pwrctrl->reg_usb_apsrc_req_mask_b & 0x1) << 22) |
+ ((pwrctrl->reg_usb_vrf18_req_mask_b & 0x1) << 23) |
+ ((pwrctrl->reg_usb_ddr_en_mask_b & 0x1) << 24) |
+ ((pwrctrl->reg_pextp_p0_srcclkena_mask_b & 0x1) << 25) |
+ ((pwrctrl->reg_pextp_p0_infra_req_mask_b & 0x1) << 26) |
+ ((pwrctrl->reg_pextp_p0_apsrc_req_mask_b & 0x1) << 27) |
+ ((pwrctrl->reg_pextp_p0_vrf18_req_mask_b & 0x1) << 28) |
+ ((pwrctrl->reg_pextp_p0_ddr_en_mask_b & 0x1) << 29));
+
+ /* SPM_SRC3_MASK */
+ write32(&mtk_spm->spm_src3_mask,
+ ((pwrctrl->reg_pextp_p1_srcclkena_mask_b & 0x1) << 0) |
+ ((pwrctrl->reg_pextp_p1_infra_req_mask_b & 0x1) << 1) |
+ ((pwrctrl->reg_pextp_p1_apsrc_req_mask_b & 0x1) << 2) |
+ ((pwrctrl->reg_pextp_p1_vrf18_req_mask_b & 0x1) << 3) |
+ ((pwrctrl->reg_pextp_p1_ddr_en_mask_b & 0x1) << 4) |
+ ((pwrctrl->reg_gce0_infra_req_mask_b & 0x1) << 5) |
+ ((pwrctrl->reg_gce0_apsrc_req_mask_b & 0x1) << 6) |
+ ((pwrctrl->reg_gce0_vrf18_req_mask_b & 0x1) << 7) |
+ ((pwrctrl->reg_gce0_ddr_en_mask_b & 0x1) << 8) |
+ ((pwrctrl->reg_gce1_infra_req_mask_b & 0x1) << 9) |
+ ((pwrctrl->reg_gce1_apsrc_req_mask_b & 0x1) << 10) |
+ ((pwrctrl->reg_gce1_vrf18_req_mask_b & 0x1) << 11) |
+ ((pwrctrl->reg_gce1_ddr_en_mask_b & 0x1) << 12) |
+ ((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 13) |
+ ((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 14) |
+ ((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 15) |
+ ((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 16) |
+ ((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 17) |
+ ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 18) |
+ ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 19) |
+ ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 20) |
+ ((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 21) |
+ ((pwrctrl->reg_disp2_apsrc_req_mask_b & 0x1) << 22) |
+ ((pwrctrl->reg_disp2_ddr_en_mask_b & 0x1) << 23) |
+ ((pwrctrl->reg_disp3_apsrc_req_mask_b & 0x1) << 24) |
+ ((pwrctrl->reg_disp3_ddr_en_mask_b & 0x1) << 25) |
+ ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 26) |
+ ((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 27));
+
+ /* SPM_SRC4_MASK */
+ write32(&mtk_spm->spm_src4_mask,
+ ((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) |
+ ((pwrctrl->reg_mcusys_merge_ddr_en_mask_b & 0x1ff) << 9) |
+ ((pwrctrl->reg_dramc_md32_infra_req_mask_b & 0x3) << 18) |
+ ((pwrctrl->reg_dramc_md32_vrf18_req_mask_b & 0x3) << 20) |
+ ((pwrctrl->reg_dramc_md32_ddr_en_mask_b & 0x3) << 22) |
+ ((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 24));
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ write32(&mtk_spm->spm_wakeup_event_mask,
+ ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ write32(&mtk_spm->spm_wakeup_event_ext_mask,
+ ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
+}
+
+void spm_register_init(void)
+{
+ /* set clock path for SPM */
+ setbits32(&mtk_topckgen->clk_scp_cfg_0, 0x7ff);
+ /* enable register control */
+ write32(&mtk_spm->poweron_config_en, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
+ /* init power control register, dram will set this register */
+ write32(&mtk_spm->spm_power_on_val1, POWER_ON_VAL1_DEF);
+ write32(&mtk_spm->pcm_pwr_io_en, 0);
+ /* reset PCM */
+ write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB |
+ PCM_SW_RESET_LSB);
+ write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
+ write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | REG_EVENT_LOCK_EN_LSB |
+ REG_SPM_SRAM_ISOINT_B_LSB |
+ RG_AHBMIF_APBEN_LSB |
+ REG_MD32_APB_INTERNAL_EN_LSB);
+ /* clean wakeup event raw status */
+ write32(&mtk_spm->spm_wakeup_event_mask, SPM_WAKEUP_EVENT_MASK_DEF);
+ /* clean ISR status */
+ write32(&mtk_spm->spm_irq_mask, ISRM_ALL);
+ write32(&mtk_spm->spm_irq_sta, ISRC_ALL);
+ write32(&mtk_spm->spm_swint_clr, PCM_SW_INT_ALL);
+ /* init r7 with POWER_ON_VAL1 */
+ write32(&mtk_spm->pcm_reg_data_ini, read32(&mtk_spm->spm_power_on_val1));
+ write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7);
+ write32(&mtk_spm->pcm_pwr_io_en, 0);
+ /* DDR EN de-bounce length to 5us */
+ write32(&mtk_spm->ddren_dbc_con, 0x154 | REG_ALL_DDR_EN_DBC_EN_LSB);
+ /* configure ARMPLL Control Mode for MCDI */
+ write32(&mtk_spm->armpll_clk_sel, 0x3FF);
+ /* init for SPM Resource ACK */
+ write32(&mtk_spm->spm_resource_ack_con0, 0xFFFFFFFF);
+ write32(&mtk_spm->spm_resource_ack_con1, 0xFFFFFFFF);
+ write32(&mtk_spm->spm_resource_ack_con2, 0xFFFFFFFF);
+ write32(&mtk_spm->spm_resource_ack_con3, 0xFFFFFFFF);
+ /* init VCORE DVFS Status */
+ write32(&mtk_spm->spm_dvfs_level, 0x00000001);
+ write32(&mtk_spm->spm_dvs_dfs_level, 0x00010001);
+ SET32_BITFIELDS(&mtk_spm->spm_dvfs_misc,
+ SPM_DVFS_FORCE_ENABLE_LSB, 0,
+ SPM_DVFSRC_ENABLE_LSB, 1);
+ write32(&mtk_spm->spm_dvfs_level, 0x00000001);
+ write32(&mtk_spm->spm_dvs_dfs_level, 0x00010001);
+ /* HW S1 state monitor */
+ write32(&mtk_spm->spm_ack_chk_sel_3, SPM_ACK_CHK_3_SEL_HW_S1);
+ write32(&mtk_spm->spm_ack_chk_timer_3, SPM_ACK_CHK_3_HW_S1_CNT);
+ spm_hw_s1_state_monitor_pause();
+}
+
+void spm_reset_and_init_pcm(void)
+{
+ uint32_t val;
+ bool first_load_fw = true;
+
+ /* check the SPM FW is run or not */
+ if (read32(&mtk_spm->md32pcm_cfgreg_sw_rstn) &
+ MD32PCM_CFGREG_SW_RSTN_RUN)
+ first_load_fw = false;
+
+ if (!first_load_fw) {
+ /* SPM code swapping */
+ spm_code_swapping();
+ /* backup PCM r0 -> SPM_POWER_ON_VAL0 before `reset PCM` */
+ write32(&mtk_spm->spm_power_on_val0,
+ read32(&mtk_spm->pcm_reg0_data));
+ }
+
+ /* disable r0 and r7 to control power */
+ write32(&mtk_spm->pcm_pwr_io_en, 0);
+
+ /* disable pcm timer after leaving FW */
+ clrsetbits32(&mtk_spm->pcm_con1, RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
+
+ /* reset PCM */
+ write32(&mtk_spm->pcm_con0,
+ SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB);
+ write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB);
+
+ /* clear SPM EVENT count */
+ setbits32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB);
+ clrsetbits32(&mtk_spm->pcm_con1, SPM_EVENT_COUNTER_CLR_LSB, SPM_REGWR_CFG_KEY);
+
+ /* init PCM_CON1 (disable PCM timer but keep PCM WDT setting) */
+ val = read32(&mtk_spm->pcm_con1) & RG_PCM_WDT_WAKE_LSB;
+ write32(&mtk_spm->pcm_con1, val | SPM_REGWR_CFG_KEY |
+ REG_EVENT_LOCK_EN_LSB |
+ REG_SPM_SRAM_ISOINT_B_LSB |
+ RG_AHBMIF_APBEN_LSB |
+ REG_MD32_APB_INTERNAL_EN_LSB);
+}
+
+void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
+{
+ uint32_t val, mask;
+
+ /* toggle event counter clear */
+ setbits32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB);
+ /* toggle for reset SYS TIMER start point */
+ SET32_BITFIELDS(&mtk_spm->sys_timer_con, SYS_TIMER_START_EN_LSB, 1);
+
+ if (pwrctrl->timer_val_cust == 0)
+ val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX;
+ else
+ val = pwrctrl->timer_val_cust;
+
+ write32(&mtk_spm->pcm_timer_val, val);
+ setbits32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB);
+
+ /* unmask AP wakeup source */
+ if (pwrctrl->wake_src_cust == 0)
+ mask = pwrctrl->wake_src;
+ else
+ mask = pwrctrl->wake_src_cust;
+
+ write32(&mtk_spm->spm_wakeup_event_mask, ~mask);
+
+ /* unmask SPM ISR (keep TWAM setting) */
+ setbits32(&mtk_spm->spm_irq_mask, ISRM_RET_IRQ_AUX);
+ /* toggle event counter clear */
+ clrsetbits32(&mtk_spm->pcm_con1, SPM_EVENT_COUNTER_CLR_LSB, SPM_REGWR_CFG_KEY);
+ /* toggle for reset SYS TIMER start point */
+ SET32_BITFIELDS(&mtk_spm->sys_timer_con, SYS_TIMER_START_EN_LSB, 0);
+}
+
+const struct pwr_ctrl *get_pwr_ctrl(void)
+{
+ return &spm_init_ctrl;
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 03:27:07 +0000