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-rw-r--r--src/cpu/amd/pi/00630F01/Kconfig8
-rw-r--r--src/cpu/amd/pi/00660F01/Kconfig8
-rw-r--r--src/cpu/amd/pi/00730F01/Kconfig8
-rw-r--r--src/northbridge/amd/pi/00630F01/northbridge.c11
-rw-r--r--src/northbridge/amd/pi/00660F01/northbridge.c11
-rw-r--r--src/northbridge/amd/pi/00730F01/northbridge.c11
-rw-r--r--src/northbridge/amd/pi/nb_common.h19
7 files changed, 37 insertions, 39 deletions
diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig
index f3ed237130..75a8441e45 100644
--- a/src/cpu/amd/pi/00630F01/Kconfig
+++ b/src/cpu/amd/pi/00630F01/Kconfig
@@ -23,14 +23,6 @@ config CPU_ADDR_BITS
int
default 48
-config CBB
- hex
- default 0x0
-
-config CDB
- hex
- default 0x18
-
config XIP_ROM_SIZE
hex
default 0x100000
diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig
index d57cfb17bf..a6eca07f44 100644
--- a/src/cpu/amd/pi/00660F01/Kconfig
+++ b/src/cpu/amd/pi/00660F01/Kconfig
@@ -23,14 +23,6 @@ config CPU_ADDR_BITS
int
default 48
-config CBB
- hex
- default 0x0
-
-config CDB
- hex
- default 0x18
-
config XIP_ROM_SIZE
hex
default 0x100000
diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig
index a455a3e677..054523ee37 100644
--- a/src/cpu/amd/pi/00730F01/Kconfig
+++ b/src/cpu/amd/pi/00730F01/Kconfig
@@ -23,14 +23,6 @@ config CPU_ADDR_BITS
int
default 40
-config CBB
- hex
- default 0x0
-
-config CDB
- hex
- default 0x18
-
config XIP_ROM_SIZE
hex
default 0x100000
diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c
index 9ce811b315..d606dc5547 100644
--- a/src/northbridge/amd/pi/00630F01/northbridge.c
+++ b/src/northbridge/amd/pi/00630F01/northbridge.c
@@ -34,6 +34,7 @@
#include <cpu/amd/mtrr.h>
#include <arch/acpigen.h>
#include <assert.h>
+#include <northbridge/amd/pi/nb_common.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
#include <northbridge/amd/pi/agesawrapper.h>
@@ -102,7 +103,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
static struct device *get_node_pci(u32 nodeid, u32 fn)
{
- return pcidev_on_root(CONFIG_CDB + nodeid, fn);
+ return pcidev_on_root(DEV_CDB + nodeid, fn);
}
static void get_fx_devs(void)
@@ -145,7 +146,7 @@ static void f1_write_config32(unsigned reg, u32 value)
static u32 amdfam15_nodeid(struct device *dev)
{
- return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
+ return (dev->path.pci.devfn >> 3) - DEV_CDB;
}
static void set_vga_enable_reg(u32 nodeid, u32 linkn)
@@ -853,9 +854,9 @@ static void cpu_bus_scan(struct device *dev)
printk(BIOS_SPEW, "KaveriPI Debug: AMD Topology Number of Modules (@0x%p) is %d\n", modules_ptr, modules);
printk(BIOS_SPEW, "KaveriPI Debug: AMD Topology Number of IOAPICs (@0x%p) is %d\n", options, (int)(options->CfgPlatNumIoApics));
- dev_mc = pcidev_on_root(CONFIG_CDB, 0);
+ dev_mc = pcidev_on_root(DEV_CDB, 0);
if (!dev_mc) {
- printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
+ printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB);
die("");
}
sysconf_init(dev_mc);
@@ -878,7 +879,7 @@ static void cpu_bus_scan(struct device *dev)
unsigned devn;
struct bus *pbus;
- devn = CONFIG_CDB + i;
+ devn = DEV_CDB + i;
pbus = dev_mc->bus;
/* Find the cpu's pci device */
diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c
index 696c6536ef..056e7012d9 100644
--- a/src/northbridge/amd/pi/00660F01/northbridge.c
+++ b/src/northbridge/amd/pi/00660F01/northbridge.c
@@ -33,6 +33,7 @@
#include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
#include <arch/acpigen.h>
+#include <northbridge/amd/pi/nb_common.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
#include <northbridge/amd/pi/agesawrapper.h>
@@ -101,7 +102,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
static struct device *get_node_pci(u32 nodeid, u32 fn)
{
- return pcidev_on_root(CONFIG_CDB + nodeid, fn);
+ return pcidev_on_root(DEV_CDB + nodeid, fn);
}
static void get_fx_devs(void)
@@ -144,7 +145,7 @@ static void f1_write_config32(unsigned reg, u32 value)
static u32 amdfam15_nodeid(struct device *dev)
{
- return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
+ return (dev->path.pci.devfn >> 3) - DEV_CDB;
}
static void set_vga_enable_reg(u32 nodeid, u32 linkn)
@@ -843,9 +844,9 @@ static void cpu_bus_scan(struct device *dev)
ioapic_count = (int)options->CfgPlatNumIoApics;
ASSERT(ioapic_count > 0);
- dev_mc = pcidev_on_root(CONFIG_CDB, 0);
+ dev_mc = pcidev_on_root(DEV_CDB, 0);
if (!dev_mc) {
- printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
+ printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB);
die("");
}
sysconf_init(dev_mc);
@@ -868,7 +869,7 @@ static void cpu_bus_scan(struct device *dev)
unsigned devn;
struct bus *pbus;
- devn = CONFIG_CDB + i;
+ devn = DEV_CDB + i;
pbus = dev_mc->bus;
/* Find the cpu's pci device */
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index ebc1ca4037..2579d370a7 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -35,6 +35,7 @@
#include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
#include <arch/acpigen.h>
+#include <northbridge/amd/pi/nb_common.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
#include <northbridge/amd/pi/agesawrapper.h>
@@ -103,7 +104,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
static struct device *get_node_pci(u32 nodeid, u32 fn)
{
- return pcidev_on_root(CONFIG_CDB + nodeid, fn);
+ return pcidev_on_root(DEV_CDB + nodeid, fn);
}
static void get_fx_devs(void)
@@ -146,7 +147,7 @@ static void f1_write_config32(unsigned reg, u32 value)
static u32 amdfam16_nodeid(struct device *dev)
{
- return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
+ return (dev->path.pci.devfn >> 3) - DEV_CDB;
}
static void set_vga_enable_reg(u32 nodeid, u32 linkn)
@@ -1089,9 +1090,9 @@ static void cpu_bus_scan(struct device *dev)
printk(BIOS_SPEW, "MullinsPI Debug: AMD Topology Number of Modules (@0x%p) is %d\n", modules_ptr, modules);
printk(BIOS_SPEW, "MullinsPI Debug: AMD Topology Number of IOAPICs (@0x%p) is %d\n", options, (int)options->CfgPlatNumIoApics);
- dev_mc = pcidev_on_root(CONFIG_CDB, 0);
+ dev_mc = pcidev_on_root(DEV_CDB, 0);
if (!dev_mc) {
- printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
+ printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB);
die("");
}
sysconf_init(dev_mc);
@@ -1114,7 +1115,7 @@ static void cpu_bus_scan(struct device *dev)
unsigned devn;
struct bus *pbus;
- devn = CONFIG_CDB + i;
+ devn = DEV_CDB + i;
pbus = dev_mc->bus;
/* Find the cpu's pci device */
diff --git a/src/northbridge/amd/pi/nb_common.h b/src/northbridge/amd/pi/nb_common.h
new file mode 100644
index 0000000000..3e78155afd
--- /dev/null
+++ b/src/northbridge/amd/pi/nb_common.h
@@ -0,0 +1,19 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __AMD_NB_COMMON_H__
+#define __AMD_NB_COMMON_H__
+
+#define DEV_CDB 0x18
+
+#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 20:44:50 +0000