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-rw-r--r--src/cpu/amd/agesa/family10/Kconfig1
-rw-r--r--src/cpu/amd/agesa/family12/Kconfig1
-rw-r--r--src/cpu/amd/agesa/family12/fixme.c7
-rw-r--r--src/cpu/amd/agesa/family14/Kconfig1
-rw-r--r--src/cpu/amd/agesa/family14/fixme.c7
-rw-r--r--src/cpu/amd/agesa/family15/Kconfig1
-rw-r--r--src/cpu/amd/agesa/family15/fixme.c7
-rw-r--r--src/cpu/amd/agesa/family15rl/Kconfig1
-rw-r--r--src/cpu/amd/agesa/family15rl/fixme.c7
-rw-r--r--src/cpu/amd/agesa/family15tn/Kconfig1
-rw-r--r--src/cpu/amd/agesa/family15tn/fixme.c7
-rw-r--r--src/cpu/amd/agesa/family16kb/Kconfig1
-rw-r--r--src/cpu/amd/agesa/family16kb/fixme.c7
13 files changed, 0 insertions, 49 deletions
diff --git a/src/cpu/amd/agesa/family10/Kconfig b/src/cpu/amd/agesa/family10/Kconfig
index 3127855842..6bb8d43260 100644
--- a/src/cpu/amd/agesa/family10/Kconfig
+++ b/src/cpu/amd/agesa/family10/Kconfig
@@ -16,7 +16,6 @@
config CPU_AMD_AGESA_FAMILY10
bool
select CPU_AMD_MODEL_10XXX
- select PCI_IO_CFG_EXT
select MMCONF_SUPPORT_DEFAULT
select X86_AMD_FIXED_MTRRS
diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig
index b15a14be21..8e4c7bad2f 100644
--- a/src/cpu/amd/agesa/family12/Kconfig
+++ b/src/cpu/amd/agesa/family12/Kconfig
@@ -15,7 +15,6 @@
config CPU_AMD_AGESA_FAMILY12
bool
- select PCI_IO_CFG_EXT
select MMCONF_SUPPORT_DEFAULT
select X86_AMD_FIXED_MTRRS
diff --git a/src/cpu/amd/agesa/family12/fixme.c b/src/cpu/amd/agesa/family12/fixme.c
index efd004af85..deeb8b9096 100644
--- a/src/cpu/amd/agesa/family12/fixme.c
+++ b/src/cpu/amd/agesa/family12/fixme.c
@@ -76,13 +76,6 @@ void amd_initmmio(void)
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
- /*
- Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
- */
- LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
- MsrReg = MsrReg | 0x0000400000000000ull;
- LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
-
/* Enable Non-Post Memory in CPU */
PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;
PciData = (PciData >> 8) & ~0xff;
diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig
index 5ac601cd66..7be63f5fcb 100644
--- a/src/cpu/amd/agesa/family14/Kconfig
+++ b/src/cpu/amd/agesa/family14/Kconfig
@@ -15,7 +15,6 @@
config CPU_AMD_AGESA_FAMILY14
bool
- select PCI_IO_CFG_EXT
select MMCONF_SUPPORT_DEFAULT
select X86_AMD_FIXED_MTRRS
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c
index 25a32bdb9c..9a171ede40 100644
--- a/src/cpu/amd/agesa/family14/fixme.c
+++ b/src/cpu/amd/agesa/family14/fixme.c
@@ -78,13 +78,6 @@ void amd_initmmio(void)
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
- /*
- Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
- */
- LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
- MsrReg = MsrReg | 0x0000400000000000ull;
- LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
-
/* Set Ontario Link Data */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0);
PciData = 0x01308002;
diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig
index eb32b70b8a..22e4d8c0f5 100644
--- a/src/cpu/amd/agesa/family15/Kconfig
+++ b/src/cpu/amd/agesa/family15/Kconfig
@@ -15,7 +15,6 @@
config CPU_AMD_AGESA_FAMILY15
bool
- select PCI_IO_CFG_EXT
select MMCONF_SUPPORT_DEFAULT
select X86_AMD_FIXED_MTRRS
diff --git a/src/cpu/amd/agesa/family15/fixme.c b/src/cpu/amd/agesa/family15/fixme.c
index 5633007e91..7b8598d816 100644
--- a/src/cpu/amd/agesa/family15/fixme.c
+++ b/src/cpu/amd/agesa/family15/fixme.c
@@ -269,13 +269,6 @@ void amd_initmmio(void)
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
- /*
- * Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
- */
- LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
- MsrReg = MsrReg | (1ULL << 46);
- LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
-
#if IS_ENABLED(CONFIG_BOARD_AMD_DINAR)
UINT32 PciData;
PCI_ADDR PciAddress;
diff --git a/src/cpu/amd/agesa/family15rl/Kconfig b/src/cpu/amd/agesa/family15rl/Kconfig
index 5948787b58..b916e2c145 100644
--- a/src/cpu/amd/agesa/family15rl/Kconfig
+++ b/src/cpu/amd/agesa/family15rl/Kconfig
@@ -16,7 +16,6 @@
config CPU_AMD_AGESA_FAMILY15_RL
bool
- select PCI_IO_CFG_EXT
select MMCONF_SUPPORT_DEFAULT
select X86_AMD_FIXED_MTRRS
diff --git a/src/cpu/amd/agesa/family15rl/fixme.c b/src/cpu/amd/agesa/family15rl/fixme.c
index b7d890392e..b35d115692 100644
--- a/src/cpu/amd/agesa/family15rl/fixme.c
+++ b/src/cpu/amd/agesa/family15rl/fixme.c
@@ -72,13 +72,6 @@ void amd_initmmio(void)
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
- /*
- Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
- */
- LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
- MsrReg = MsrReg | 0x0000400000000000;
- LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
-
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig
index 3f8a3f07c2..1f41560a4d 100644
--- a/src/cpu/amd/agesa/family15tn/Kconfig
+++ b/src/cpu/amd/agesa/family15tn/Kconfig
@@ -15,7 +15,6 @@
config CPU_AMD_AGESA_FAMILY15_TN
bool
- select PCI_IO_CFG_EXT
select MMCONF_SUPPORT_DEFAULT
select X86_AMD_FIXED_MTRRS
diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c
index b7d890392e..b35d115692 100644
--- a/src/cpu/amd/agesa/family15tn/fixme.c
+++ b/src/cpu/amd/agesa/family15tn/fixme.c
@@ -72,13 +72,6 @@ void amd_initmmio(void)
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
- /*
- Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
- */
- LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
- MsrReg = MsrReg | 0x0000400000000000;
- LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
-
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig
index 1af9561878..3f65055275 100644
--- a/src/cpu/amd/agesa/family16kb/Kconfig
+++ b/src/cpu/amd/agesa/family16kb/Kconfig
@@ -15,7 +15,6 @@
config CPU_AMD_AGESA_FAMILY16_KB
bool
- select PCI_IO_CFG_EXT
select MMCONF_SUPPORT_DEFAULT
select X86_AMD_FIXED_MTRRS
diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c
index da2bcd9cba..d1bc4bc55f 100644
--- a/src/cpu/amd/agesa/family16kb/fixme.c
+++ b/src/cpu/amd/agesa/family16kb/fixme.c
@@ -72,13 +72,6 @@ void amd_initmmio(void)
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
- /*
- Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
- */
- LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
- MsrReg = MsrReg | 0x0000400000000000;
- LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
-
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 19:28:49 +0000