diff options
| -rw-r--r-- | src/cpu/amd/agesa/Kconfig | 9 | ||||
| -rw-r--r-- | src/cpu/amd/agesa/Makefile.inc | 15 | ||||
| -rw-r--r-- | src/drivers/amd/agesa/oem_s3.c | 80 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/Kconfig | 1 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/Kconfig | 1 |
5 files changed, 22 insertions, 84 deletions
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 8c383a5f13..e4f15960e1 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -13,6 +13,7 @@ config CPU_AMD_AGESA select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME select SSE2 + select CACHE_MRC_SETTINGS if CPU_AMD_AGESA @@ -44,14 +45,6 @@ config ENABLE_MRC_CACHE Try to restore memory training results from non-volatile memory. -config S3_DATA_POS - hex - default 0xFFFF0000 - -config S3_DATA_SIZE - int - default 4096 - endif # CPU_AMD_AGESA source "src/cpu/amd/agesa/family14/Kconfig" diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 14067e1fed..1f9cca50c9 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -3,18 +3,3 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb - -ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) - -$(obj)/coreboot_s3nv.rom: $(obj)/config.h - echo " S3 NVRAM $(CONFIG_S3_DATA_POS) (S3 storage area)" - # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) - printf %d $(CONFIG_S3_DATA_SIZE) | LC_ALL=C awk '{for (i=0; i<$$1; i++) {printf "%c", 255}}' > $@.tmp - mv $@.tmp $@ - -cbfs-files-y += s3nv -s3nv-file := $(obj)/coreboot_s3nv.rom -s3nv-position := $(CONFIG_S3_DATA_POS) -s3nv-type := raw - -endif # CONFIG_HAVE_ACPI_RESUME == y diff --git a/src/drivers/amd/agesa/oem_s3.c b/src/drivers/amd/agesa/oem_s3.c index 9220f3e0ce..cd5e858f0e 100644 --- a/src/drivers/amd/agesa/oem_s3.c +++ b/src/drivers/amd/agesa/oem_s3.c @@ -1,41 +1,32 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <spi-generic.h> -#include <spi_flash.h> #include <string.h> #include <cbmem.h> #include <console/console.h> +#include <mrc_cache.h> #include <northbridge/amd/agesa/state_machine.h> #include <AGESA.h> #include <northbridge/amd/agesa/agesa_helper.h> -/* The size needs to be 4k aligned, which is the sector size of most flashes. */ -#define S3_DATA_NONVOLATILE_SIZE 0x1000 - -#if CONFIG(HAVE_ACPI_RESUME) && S3_DATA_NONVOLATILE_SIZE > CONFIG_S3_DATA_SIZE -#error "Please increase the value of S3_DATA_SIZE" -#endif - -static void get_s3nv_data(uintptr_t *pos, uintptr_t *len) -{ - /* FIXME: Find file from CBFS. */ - *pos = CONFIG_S3_DATA_POS; - *len = S3_DATA_NONVOLATILE_SIZE; -} +/* Training data versioning is not supported or tracked. */ +#define DEFAULT_MRC_VERSION 0 AGESA_STATUS OemInitResume(AMD_S3_PARAMS *dataBlock) { - uintptr_t pos, size; - get_s3nv_data(&pos, &size); + void *nv_storage = NULL; + size_t nv_storage_size = 0; - u32 len = *(u32*)pos; + nv_storage = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, DEFAULT_MRC_VERSION, + &nv_storage_size); - /* Test for uninitialized s3nv data in SPI. */ - if (len == 0 || len == (u32)-1ULL) - return AGESA_FATAL; + if (nv_storage == NULL || nv_storage_size == 0) { + printk(BIOS_ERR, "%s: No valid MRC cache!\n", __func__); + return AGESA_CRITICAL; + } + + dataBlock->NvStorage = nv_storage; + dataBlock->NvStorageSize = nv_storage_size; - dataBlock->NvStorageSize = len; - dataBlock->NvStorage = (void *) (pos + sizeof(u32)); return AGESA_SUCCESS; } @@ -56,44 +47,13 @@ AGESA_STATUS OemS3LateRestore(AMD_S3_PARAMS *dataBlock) return AGESA_SUCCESS; } -#if ENV_RAMSTAGE - -static int spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len) -{ -#if CONFIG(SPI_FLASH) - struct spi_flash flash; - - spi_init(); - if (spi_flash_probe(0, 0, &flash)) - return -1; - - spi_flash_volatile_group_begin(&flash); - - spi_flash_erase(&flash, pos, size); - spi_flash_write(&flash, pos, sizeof(len), &len); - spi_flash_write(&flash, pos + sizeof(len), len, buf); - - spi_flash_volatile_group_end(&flash); - return 0; -#else - return -1; -#endif -} - AGESA_STATUS OemS3Save(AMD_S3_PARAMS *dataBlock) { - uintptr_t pos, size; - - /* To be consumed in AmdInitResume. */ - get_s3nv_data(&pos, &size); - if (size && dataBlock->NvStorageSize) - spi_SaveS3info(pos, size, dataBlock->NvStorage, - dataBlock->NvStorageSize); - else - printk(BIOS_EMERG, - "Error: Cannot store memory training results in SPI.\n" - "Error: S3 resume will not be possible.\n" - ); + if (mrc_cache_stash_data(MRC_TRAINING_DATA, DEFAULT_MRC_VERSION, + dataBlock->NvStorage, dataBlock->NvStorageSize) < 0) { + printk(BIOS_ERR, "%s: Failed to stash MRC data\n", __func__); + return AGESA_CRITICAL; + } /* To be consumed in AmdS3LateRestore. */ char *heap = cbmem_add(CBMEM_ID_RESUME_SCRATCH, HIGH_MEMORY_SCRATCH); @@ -107,5 +67,3 @@ AGESA_STATUS OemS3Save(AMD_S3_PARAMS *dataBlock) return AGESA_SUCCESS; } - -#endif /* ENV_RAMSTAGE */ diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 072f3fd53f..5ea6b1a2e0 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -17,6 +17,7 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM select SOC_AMD_COMMON_BLOCK_PCI_MMCONF + select BOOT_DEVICE_SUPPORTS_WRITES config EHCI_BAR hex diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index fcfdfb4a68..7ab2cc1c07 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -11,6 +11,7 @@ config SOUTHBRIDGE_AMD_CIMX_SB800 select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM select SOC_AMD_COMMON_BLOCK_PCI_MMCONF + select BOOT_DEVICE_SUPPORTS_WRITES if SOUTHBRIDGE_AMD_CIMX_SB800 config ENABLE_IDE_COMBINED_MODE |