diff options
| -rw-r--r-- | src/mainboard/google/herobrine/mainboard.c | 26 | ||||
| -rw-r--r-- | src/soc/qualcomm/common/include/soc/pcie.h | 1 |
2 files changed, 27 insertions, 0 deletions
diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c index ece6d6859a..2648392227 100644 --- a/src/mainboard/google/herobrine/mainboard.c +++ b/src/mainboard/google/herobrine/mainboard.c @@ -8,10 +8,12 @@ #include <delay.h> #include <device/device.h> #include <device/mmio.h> +#include <ec/google/chromeec/ec.h> #include <edid.h> #include <soc/clock.h> #include <soc/display/mdssreg.h> #include <soc/display/edp_ctrl.h> +#include <soc/pcie.h> #include <soc/qupv3_config_common.h> #include <soc/qup_se_handlers_common.h> #include <soc/qcom_qup_se.h> @@ -82,6 +84,30 @@ static void display_startup(void) } } +/* + * Determine if board need to perform PCIe initialization. On Herobrine, + * resistor strapping will be such that bit 0 will be assigned 2 (high Z) if it + * is an NVMe enabled platform. + */ +bool mainboard_needs_pcie_init(void) +{ + uint32_t sku = sku_id(); + + if (sku == CROS_SKU_UNKNOWN) { + printk(BIOS_WARNING, "Unknown SKU (%#x); assuming PCIe", sku); + return true; + } else if (sku == CROS_SKU_UNPROVISIONED) { + printk(BIOS_WARNING, "Unprovisioned SKU (%#x); assuming PCIe", sku); + return true; + } + + if ((sku % 3) == 2) + return true; + + /* Otherwise, eMMC */ + return false; +} + static void mainboard_init(struct device *dev) { /* Configure clock for eMMC */ diff --git a/src/soc/qualcomm/common/include/soc/pcie.h b/src/soc/qualcomm/common/include/soc/pcie.h index 09ea6712dc..b2f9e45a3d 100644 --- a/src/soc/qualcomm/common/include/soc/pcie.h +++ b/src/soc/qualcomm/common/include/soc/pcie.h @@ -221,5 +221,6 @@ void gcom_pcie_power_on_ep(void); void gcom_pcie_get_config(struct qcom_pcie_cntlr_t *host_cfg); void qcom_pci_domain_read_resources(struct device *dev); void qcom_setup_pcie_host(struct device *dev); +bool mainboard_needs_pcie_init(void); #endif |