diff options
| -rw-r--r-- | src/Kconfig | 4 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_0/Kconfig | 9 | ||||
| -rw-r--r-- | src/include/cpu/x86/mtrr.h | 47 | ||||
| -rw-r--r-- | src/mainboard/adi/rcc-dff/Kconfig | 4 | ||||
| -rw-r--r-- | src/mainboard/esd/atom15/Kconfig | 4 | ||||
| -rw-r--r-- | src/mainboard/intel/bayleybay_fsp/Kconfig | 4 | ||||
| -rw-r--r-- | src/mainboard/intel/camelbackmountain_fsp/Kconfig | 4 | ||||
| -rw-r--r-- | src/mainboard/intel/minnowmax/Kconfig | 4 | ||||
| -rw-r--r-- | src/mainboard/intel/mohonpeak/Kconfig | 4 | ||||
| -rw-r--r-- | src/mainboard/ocp/monolake/Kconfig | 4 | ||||
| -rw-r--r-- | src/mainboard/ocp/wedge100s/Kconfig | 4 | ||||
| -rw-r--r-- | src/mainboard/siemens/mc_bdx1/Kconfig | 4 | ||||
| -rw-r--r-- | src/mainboard/siemens/mc_tcu3/Kconfig | 4 |
13 files changed, 25 insertions, 75 deletions
diff --git a/src/Kconfig b/src/Kconfig index d2b9fc23b6..4c1a0da708 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -516,10 +516,6 @@ config IOAPIC bool default n -config CACHE_ROM_SIZE_OVERRIDE - hex - default 0x0 - config USE_WATCHDOG_ON_BOOT bool default n diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig index 6aa89491e4..c7f6c18f86 100644 --- a/src/drivers/intel/fsp1_0/Kconfig +++ b/src/drivers/intel/fsp1_0/Kconfig @@ -103,15 +103,6 @@ config VIRTUAL_ROM_SIZE the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM size is 16 MB. -config CACHE_ROM_SIZE_OVERRIDE - hex "Cache ROM Size" - default CBFS_SIZE - help - This is the size of the cachable area that is passed into the FSP in - the early initialization. Typically this should be the size of the CBFS - area, but the size must be a power of 2 whereas the CBFS size does not - have this limitation. - config USE_GENERIC_FSP_CAR_INC bool default n diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 0d64be517e..f1e067a26b 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -118,12 +118,15 @@ static inline unsigned int fls(unsigned int x) } #endif /* !defined(__ASSEMBLER__) && !defined(__ROMCC__) */ -/* Align up to next power of 2, suitable for ROMCC and assembler too. - * Range of result 256kB to 128MB is good enough here. - */ +/* Align up/down to next power of 2, suitable for ROMCC and assembler + too. Range of result 256kB to 128MB is good enough here. */ #define _POW2_MASK(x) ((x>>1)|(x>>2)|(x>>3)|(x>>4)|(x>>5)| \ (x>>6)|(x>>7)|(x>>8)|((1<<18)-1)) #define _ALIGN_UP_POW2(x) ((x + _POW2_MASK(x)) & ~_POW2_MASK(x)) +#define _ALIGN_DOWN_POW2(x) ((x) & ~_POW2_MASK(x)) + +/* Calculate `4GiB - x` (e.g. absolute address for offset from 4GiB) */ +#define _FROM_4G_TOP(x) (((1 << 20) - ((x) >> 12)) << 12) /* At the end of romstage, low RAM 0..CACHE_TM_RAMTOP may be set * as write-back cacheable to speed up ramstage decompression. @@ -135,29 +138,29 @@ static inline unsigned int fls(unsigned int x) # error "CONFIG_XIP_ROM_SIZE is not a power of 2" #endif -/* Select CACHE_ROM_SIZE to use with MTRR setup. For most cases this - * resolves to a suitable CONFIG_ROM_SIZE but some odd cases need to - * use CONFIG_CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig. - */ -#if (CONFIG_CACHE_ROM_SIZE_OVERRIDE != 0) -# define CACHE_ROM_SIZE CONFIG_CACHE_ROM_SIZE_OVERRIDE -#else -# if ((CONFIG_ROM_SIZE & (CONFIG_ROM_SIZE-1)) == 0) -# define CACHE_ROM_SIZE CONFIG_ROM_SIZE -# else -# define CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE) -# if (CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || (CACHE_ROM_SIZE >= \ - (2 * CONFIG_ROM_SIZE)) -# error "CACHE_ROM_SIZE is not optimal." -# endif -# endif +/* For ROM caching, generally, try to use the next power of 2. */ +#define OPTIMAL_CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE) +#define OPTIMAL_CACHE_ROM_BASE _FROM_4G_TOP(OPTIMAL_CACHE_ROM_SIZE) +#if (OPTIMAL_CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || \ + (OPTIMAL_CACHE_ROM_SIZE >= (2 * CONFIG_ROM_SIZE)) +# error "Optimal CACHE_ROM_SIZE can't be derived, _POW2_MASK needs refinement." #endif -#if ((CACHE_ROM_SIZE & (CACHE_ROM_SIZE-1)) != 0) -# error "CACHE_ROM_SIZE is not a power of 2." +/* Make sure it doesn't overlap CAR, though. If the gap between + CAR and 4GiB is too small, make it at most the size of this + gap. As we can't align up (might overlap again), align down + to get a power of 2 again, for a single MTRR. */ +#define CAR_END (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) +#if CAR_END > OPTIMAL_CACHE_ROM_BASE +# define CACHE_ROM_SIZE _ALIGN_DOWN_POW2(_FROM_4G_TOP(CAR_END)) +#else +# define CACHE_ROM_SIZE OPTIMAL_CACHE_ROM_SIZE +#endif +#if ((CACHE_ROM_SIZE & (CACHE_ROM_SIZE - 1)) != 0) +# error "CACHE_ROM_SIZE is not a power of 2, _POW2_MASK needs refinement." #endif -#define CACHE_ROM_BASE (((1<<20) - (CACHE_ROM_SIZE>>12))<<12) +#define CACHE_ROM_BASE _FROM_4G_TOP(CACHE_ROM_SIZE) #if (IS_ENABLED(CONFIG_SOC_SETS_MSRS) && !defined(__ASSEMBLER__) \ && !defined(__ROMCC__)) diff --git a/src/mainboard/adi/rcc-dff/Kconfig b/src/mainboard/adi/rcc-dff/Kconfig index b3559346b3..0673446bd3 100644 --- a/src/mainboard/adi/rcc-dff/Kconfig +++ b/src/mainboard/adi/rcc-dff/Kconfig @@ -37,10 +37,6 @@ config MAX_CPUS int default 16 -config CACHE_ROM_SIZE_OVERRIDE - hex - default 0x800000 - config FSP_FILE string default "../intel/fsp/rangeley/FvFsp.bin" diff --git a/src/mainboard/esd/atom15/Kconfig b/src/mainboard/esd/atom15/Kconfig index 814177e3e6..8568c5169a 100644 --- a/src/mainboard/esd/atom15/Kconfig +++ b/src/mainboard/esd/atom15/Kconfig @@ -36,10 +36,6 @@ config MAX_CPUS int default 16 -config CACHE_ROM_SIZE_OVERRIDE - hex - default 0x800000 - config FSP_FILE string default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig index e8318cb0f2..7f74342427 100644 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig +++ b/src/mainboard/intel/bayleybay_fsp/Kconfig @@ -38,10 +38,6 @@ config MAX_CPUS int default 16 -config CACHE_ROM_SIZE_OVERRIDE - hex - default 0x800000 - config FSP_FILE string default "../intel/fsp/baytrail/BAYTRAIL_FSP_ECC.fd" if BOARD_INTEL_BAKERSPORT_FSP diff --git a/src/mainboard/intel/camelbackmountain_fsp/Kconfig b/src/mainboard/intel/camelbackmountain_fsp/Kconfig index 3d29e2e3c4..295091f889 100644 --- a/src/mainboard/intel/camelbackmountain_fsp/Kconfig +++ b/src/mainboard/intel/camelbackmountain_fsp/Kconfig @@ -23,10 +23,6 @@ config IRQ_SLOT_COUNT int default 18 -config CACHE_ROM_SIZE_OVERRIDE - hex - default 0x800000 - config CBFS_SIZE hex default 0x00200000 diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig index f0c4526f6a..4f7d25da0c 100644 --- a/src/mainboard/intel/minnowmax/Kconfig +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -36,10 +36,6 @@ config MAX_CPUS int default 16 -config CACHE_ROM_SIZE_OVERRIDE - hex - default 0x800000 - config FSP_FILE string default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig index 207944e6c2..3a7538f3e8 100644 --- a/src/mainboard/intel/mohonpeak/Kconfig +++ b/src/mainboard/intel/mohonpeak/Kconfig @@ -37,10 +37,6 @@ config MAX_CPUS int default 16 -config CACHE_ROM_SIZE_OVERRIDE - hex - default 0x800000 - config FSP_FILE string default "../intel/fsp/rangeley/FvFsp.bin" diff --git a/src/mainboard/ocp/monolake/Kconfig b/src/mainboard/ocp/monolake/Kconfig index 2f253f0cee..09678c7053 100644 --- a/src/mainboard/ocp/monolake/Kconfig +++ b/src/mainboard/ocp/monolake/Kconfig @@ -23,10 +23,6 @@ config IRQ_SLOT_COUNT int default 18 -config CACHE_ROM_SIZE_OVERRIDE - hex - default 0x800000 - config CBFS_SIZE hex default 0x00200000 diff --git a/src/mainboard/ocp/wedge100s/Kconfig b/src/mainboard/ocp/wedge100s/Kconfig index dfdc55222e..6a33edbc0d 100644 --- a/src/mainboard/ocp/wedge100s/Kconfig +++ b/src/mainboard/ocp/wedge100s/Kconfig @@ -24,10 +24,6 @@ config IRQ_SLOT_COUNT int default 18 -config CACHE_ROM_SIZE_OVERRIDE - hex - default 0x800000 - config CBFS_SIZE hex default 0x00200000 diff --git a/src/mainboard/siemens/mc_bdx1/Kconfig b/src/mainboard/siemens/mc_bdx1/Kconfig index a24d09dc19..667a6ee688 100644 --- a/src/mainboard/siemens/mc_bdx1/Kconfig +++ b/src/mainboard/siemens/mc_bdx1/Kconfig @@ -27,10 +27,6 @@ config IRQ_SLOT_COUNT int default 18 -config CACHE_ROM_SIZE_OVERRIDE - hex - default 0x1000000 - config CBFS_SIZE hex default 0x00D00000 diff --git a/src/mainboard/siemens/mc_tcu3/Kconfig b/src/mainboard/siemens/mc_tcu3/Kconfig index 6a3b3c4594..4be0060703 100644 --- a/src/mainboard/siemens/mc_tcu3/Kconfig +++ b/src/mainboard/siemens/mc_tcu3/Kconfig @@ -44,10 +44,6 @@ config MAX_CPUS int default 16 -config CACHE_ROM_SIZE_OVERRIDE - hex - default 0x1000000 - config CBFS_SIZE hex default 0x00e00000 |