diff options
| -rw-r--r-- | src/mainboard/ocp/deltalake/devicetree.cb | 6 | ||||
| -rw-r--r-- | src/mainboard/ocp/deltalake/romstage.c | 15 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/chip.h | 25 |
3 files changed, 46 insertions, 0 deletions
diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb index f1b201d5f4..cc17e06f6c 100644 --- a/src/mainboard/ocp/deltalake/devicetree.cb +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -39,6 +39,12 @@ chip soc/intel/xeon_sp/cpx register "gen1_dec" = "0x00fc0601" # BIC in-band update support register "gen2_dec" = "0x000c0ca1" # IPMI KCS + # configure PCH PCIe port + register "pch_pci_port[8]" = "{ + .ForceEnable = 0x1, + .PortLinkSpeed = PcieAuto, + }" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index 9ce06ad616..2c8dc5efa2 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -7,6 +7,7 @@ #include <FspmUpd.h> #include <soc/romstage.h> +#include "chip.h" #include "ipmi.h" #include "vpd.h" @@ -74,7 +75,21 @@ static void mainboard_config_gpios(FSPM_UPD *mupd) static void mainboard_config_iio(FSPM_UPD *mupd) { + uint8_t index; + const config_t *config = config_of_soc(); + oem_update_iio(mupd); + + for (index = 0; index < MAX_PCH_PCIE_PORT; index++) { + mupd->FspmConfig.PchPcieForceEnable[index] = + config->pch_pci_port[index].ForceEnable; + mupd->FspmConfig.PchPciePortLinkSpeed[index] = + config->pch_pci_port[index].PortLinkSpeed; + } + + mupd->FspmConfig.PchPcieRootPortFunctionSwap = 0x00; + /* The default value is 0XFF in FSP, set it to 0xFE by platform */ + mupd->FspmConfig.PchPciePllSsc = 0xFE; } void mainboard_memory_init_params(FSPM_UPD *mupd) diff --git a/src/soc/intel/xeon_sp/cpx/chip.h b/src/soc/intel/xeon_sp/cpx/chip.h index 61e806e473..e46f34f653 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.h +++ b/src/soc/intel/xeon_sp/cpx/chip.h @@ -7,10 +7,35 @@ #include <soc/irq.h> #include <stdint.h> +#define MAX_PCH_PCIE_PORT 20 + +/** + UPD_PCH_PCIE_PORT: + ForceEnable - Enable/Disable PCH PCIe port + PortLinkSpeed - Port Link Speed. Use PCIE_LINK_SPEED to set +**/ +struct pch_pcie_port { + uint8_t ForceEnable; + uint8_t PortLinkSpeed; +}; + +/** + PCIe Link Speed Selection + **/ +typedef enum { + PcieAuto = 0, + PcieGen1, + PcieGen2, + PcieGen3 +} pcie_link_speed; + struct soc_intel_xeon_sp_cpx_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; + /* Struct for configuring PCH PCIe port */ + struct pch_pcie_port pch_pci_port[MAX_PCH_PCIE_PORT]; + /** * Interrupt Routing configuration * If bit7 is 1, the interrupt is disabled. |