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-rw-r--r--Makefile.inc4
-rw-r--r--src/include/program_loading.h7
-rw-r--r--src/lib/prog_loaders.c8
3 files changed, 19 insertions, 0 deletions
diff --git a/Makefile.inc b/Makefile.inc
index b784f3eee8..f14bc1eb39 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -1214,6 +1214,10 @@ cbfs-files-$(CONFIG_HAVE_RAMSTAGE) += $(CONFIG_CBFS_PREFIX)/ramstage
$(CONFIG_CBFS_PREFIX)/ramstage-file := $(RAMSTAGE)
$(CONFIG_CBFS_PREFIX)/ramstage-type := stage
$(CONFIG_CBFS_PREFIX)/ramstage-compression := $(CBFS_COMPRESS_FLAG)
+# The AMD LPC SPI DMA controller requires source files to be 64 byte aligned.
+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y)
+$(CONFIG_CBFS_PREFIX)/ramstage-align := 64
+endif
cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode
$(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB)
diff --git a/src/include/program_loading.h b/src/include/program_loading.h
index 5b9a94df06..ba42465046 100644
--- a/src/include/program_loading.h
+++ b/src/include/program_loading.h
@@ -145,6 +145,13 @@ int legacy_romstage_select_and_load(struct prog *romstage);
* RAMSTAGE LOADING *
************************/
+/*
+ * Asynchronously preloads ramstage.
+ *
+ * This should be called early on to allow ramstage to load before
+ * `run_ramstage` is called.
+ */
+void preload_ramstage(void);
/* Run ramstage from romstage. */
void run_ramstage(void);
diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c
index 8ad646a10c..878f729ef9 100644
--- a/src/lib/prog_loaders.c
+++ b/src/lib/prog_loaders.c
@@ -75,7 +75,15 @@ static int load_relocatable_ramstage(struct prog *ramstage)
return rmodule_stage_load(&rmod_ram);
}
+void preload_ramstage(void)
+{
+ if (!CONFIG(CBFS_PRELOAD))
+ return;
+ printk(BIOS_DEBUG, "Preloading ramstage\n");
+
+ cbfs_preload(CONFIG_CBFS_PREFIX "/ramstage");
+}
void run_ramstage(void)
{
struct prog ramstage =