diff options
| -rw-r--r-- | src/soc/intel/cannonlake/bootblock/bootblock.c | 5 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/bootblock/pch.c | 7 |
2 files changed, 7 insertions, 5 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index dfa0bd00b5..1354c43a22 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -61,11 +61,6 @@ void bootblock_soc_early_init(void) void bootblock_soc_init(void) { - /* - * Clear the GPI interrupt status and enable registers. These - * registers do not get reset to default state when booting from S5. - */ - gpi_clear_int_cfg(); report_platform_info(); bootblock_pch_init(); diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 51f8fb59f6..a4f47c990b 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -6,6 +6,7 @@ #include <device/pci_ops.h> #include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/gpio.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/p2sb.h> @@ -132,6 +133,12 @@ void pch_early_iorange_init(void) void bootblock_pch_init(void) { /* + * Clear the GPI interrupt status and enable registers. These + * registers do not get reset to default state when booting from S5. + */ + gpi_clear_int_cfg(); + + /* * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, * GPE0_STS, GPE0_EN registers. */ |