diff options
6 files changed, 42 insertions, 41 deletions
diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index 283f0e0841..f295271596 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -132,6 +132,12 @@ static void mainboard_configure_gpios(void) override_num_gpios); } +static void mainboard_devtree_update(void) +{ + variant_audio_update(); + variant_devtree_update(); +} + static void mainboard_init(void *chip_info) { const struct sci_source *gpes; @@ -145,7 +151,7 @@ static void mainboard_init(void *chip_info) mainboard_configure_gpios(); /* Update DUT configuration */ - variant_devtree_update(); + mainboard_devtree_update(); /* * Some platforms use SCI not generated by a GPIO pin (event above 23). diff --git a/src/mainboard/google/zork/variants/baseboard/Makefile.inc b/src/mainboard/google/zork/variants/baseboard/Makefile.inc index c09fc7ebb7..2b0ee3cbd8 100644 --- a/src/mainboard/google/zork/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/zork/variants/baseboard/Makefile.inc @@ -23,6 +23,7 @@ ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += fsps_baseboard_dalboz.c ramstage-y += helpers.c ramstage-y += tpm_tis.c +ramstage-y += ramstage_common.c smm-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c smm-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/devicetree.cb index 3cc311b171..93247492ed 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree.cb @@ -16,6 +16,16 @@ chip soc/amd/picasso register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" + # DMIC select GPIO for ACP machine device + # This GPIO is used to select DMIC0 or DMIC1 by the kernel driver. It does not + # really have a polarity since low and high control the selection of DMIC and + # hence does not have an active polarity. + # Kernel driver does not use the polarity field and instead treats the GPIO + # selection as follows: + # Set low (0) = Select DMIC0 + # Set high (1) = Select DMIC1 + register "dmic_select_gpio" = "ACPI_GPIO_OUTPUT(GPIO_67)" + # Start : OPN Performance Configuration # (Configuratin that is common for all variants) # For the below fields, 0 indicates use SOC default diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/audio.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/audio.asl index ae5663e7c7..b892570a7f 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/audio.asl +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/audio.asl @@ -3,43 +3,3 @@ Scope (EC0.CREC) { #include <ec/google/chromeec/acpi/codec.asl> } - -/* machine driver */ -Device (I2SM) -{ - Name (_HID, "AMDI5682") - Name (_UID, 1) - Name (_DDN, "I2S machine Driver") - - Name (_CRS, ResourceTemplate () - { -#if CONFIG(BOARD_GOOGLE_BASEBOARD_DALBOZ) - /* DMIC select GPIO */ - GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, - IoRestrictionNone, "\\_SB.GPIO", 0x00, - ResourceConsumer,,) { 6 } -#else - /* DMIC select GPIO */ - GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, - IoRestrictionNone, "\\_SB.GPIO", 0x00, - ResourceConsumer,,) { 13 } -#endif - }) - /* Device-Specific Data */ - Name (_DSD, Package () - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () - { - "dmic-gpio", Package () { ^I2SM, 0, 0, 0 } - } - } - - }) - Method (_STA) - { - Return (0xF) - } -} diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 6c5b95b5cc..c3986bcbf8 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -35,6 +35,8 @@ const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ); void variant_romstage_entry(void); /* Modify devictree settings during ramstage. */ void variant_devtree_update(void); +/* Update audio configuration in devicetree during ramstage. */ +void variant_audio_update(void); /* Configure PCIe power and reset lines as per variant sequencing requirements. */ void variant_pcie_power_reset_configure(void); diff --git a/src/mainboard/google/zork/variants/baseboard/ramstage_common.c b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c new file mode 100644 index 0000000000..6372af6a88 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi_device.h> +#include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> +#include <soc/gpio.h> + +void variant_audio_update(void) +{ + struct soc_amd_picasso_config *cfg = config_of_soc(); + uint32_t board_version; + struct acpi_gpio *gpio = &cfg->dmic_select_gpio; + + if (!google_chromeec_cbi_get_board_version(&board_version) && + (board_version >= CONFIG_VARIANT_MIN_BOARD_ID_V3_SCHEMATICS)) + return; + + if (CONFIG(BOARD_GOOGLE_BASEBOARD_TREMBYLE)) + gpio->pins[0] = GPIO_13; + else + gpio->pins[0] = GPIO_6; +} |